Struct RegCoreClr 

#[repr(transparent)]
pub struct RegCoreClr(pub u32);

Digital Regulator Core Register

Tuple Fields

0: u32

Implementations

impl RegCoreClr

pub const fn reg0_targ(&self) -> RegCoreClrReg0Targ

This field defines the target voltage for the Arm core power domain

pub const fn set_reg0_targ(&mut self, val: RegCoreClrReg0Targ)

This field defines the target voltage for the Arm core power domain

pub const fn reg0_adj(&self) -> RegCoreClrReg0Adj

This bit field defines the adjustment bits to calibrate the target value of Reg0. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register.

pub const fn set_reg0_adj(&mut self, val: RegCoreClrReg0Adj)

This bit field defines the adjustment bits to calibrate the target value of Reg0. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register.

pub const fn reg1_targ(&self) -> RegCoreClrReg1Targ

This bit field defines the target voltage for the vpu/gpu power domain. Single bit increments reflect 25mV core voltage steps. Not all steps will make sense to use either because of input supply limitations or load operation.

pub const fn set_reg1_targ(&mut self, val: RegCoreClrReg1Targ)

This bit field defines the target voltage for the vpu/gpu power domain. Single bit increments reflect 25mV core voltage steps. Not all steps will make sense to use either because of input supply limitations or load operation.

pub const fn reg1_adj(&self) -> RegCoreClrReg1Adj

This bit field defines the adjustment bits to calibrate the target value of Reg1. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register.

pub const fn set_reg1_adj(&mut self, val: RegCoreClrReg1Adj)

This bit field defines the adjustment bits to calibrate the target value of Reg1. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register.

pub const fn reg2_targ(&self) -> RegCoreClrReg2Targ

This field defines the target voltage for the SOC power domain

pub const fn set_reg2_targ(&mut self, val: RegCoreClrReg2Targ)

This field defines the target voltage for the SOC power domain

pub const fn reg2_adj(&self) -> RegCoreClrReg2Adj

This bit field defines the adjustment bits to calibrate the target value of Reg2. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register.

pub const fn set_reg2_adj(&mut self, val: RegCoreClrReg2Adj)

This bit field defines the adjustment bits to calibrate the target value of Reg2. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register.

pub const fn ramp_rate(&self) -> RegCoreClrRampRate

Regulator voltage ramp rate.

pub const fn set_ramp_rate(&mut self, val: RegCoreClrRampRate)

Regulator voltage ramp rate.

pub const fn fet_odrive(&self) -> bool

If set, increases the gate drive on power gating FETs to reduce leakage in the off state

pub const fn set_fet_odrive(&mut self, val: bool)

If set, increases the gate drive on power gating FETs to reduce leakage in the off state

Trait Implementations

impl Clone for RegCoreClr

fn clone(&self) -> RegCoreClr

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for RegCoreClr

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Default for RegCoreClr

fn default() -> RegCoreClr

Returns the “default value” for a type.

impl PartialEq for RegCoreClr

fn eq(&self, other: &RegCoreClr) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for RegCoreClr

impl Eq for RegCoreClr

impl StructuralPartialEq for RegCoreClr