#[repr(transparent)]pub struct Cdcdr(pub u32);Expand description
CCM D1 Clock Divider Register
Tuple Fields§
§0: u32Implementations§
Source§impl Cdcdr
impl Cdcdr
Sourcepub const fn flexio1_clk_sel(&self) -> Flexio1ClkSel
pub const fn flexio1_clk_sel(&self) -> Flexio1ClkSel
Selector for flexio1 clock multiplexer
Sourcepub const fn set_flexio1_clk_sel(&mut self, val: Flexio1ClkSel)
pub const fn set_flexio1_clk_sel(&mut self, val: Flexio1ClkSel)
Selector for flexio1 clock multiplexer
Sourcepub const fn flexio1_clk_podf(&self) -> Flexio1ClkPodf
pub const fn flexio1_clk_podf(&self) -> Flexio1ClkPodf
Divider for flexio1 clock podf. Divider should be updated when output clock is gated.
Sourcepub const fn set_flexio1_clk_podf(&mut self, val: Flexio1ClkPodf)
pub const fn set_flexio1_clk_podf(&mut self, val: Flexio1ClkPodf)
Divider for flexio1 clock podf. Divider should be updated when output clock is gated.
Sourcepub const fn flexio1_clk_pred(&self) -> Flexio1ClkPred
pub const fn flexio1_clk_pred(&self) -> Flexio1ClkPred
Divider for flexio1 clock pred. Divider should be updated when output clock is gated.
Sourcepub const fn set_flexio1_clk_pred(&mut self, val: Flexio1ClkPred)
pub const fn set_flexio1_clk_pred(&mut self, val: Flexio1ClkPred)
Divider for flexio1 clock pred. Divider should be updated when output clock is gated.
Sourcepub const fn spdif0_clk_sel(&self) -> Spdif0ClkSel
pub const fn spdif0_clk_sel(&self) -> Spdif0ClkSel
Selector for spdif0 clock multiplexer
Sourcepub const fn set_spdif0_clk_sel(&mut self, val: Spdif0ClkSel)
pub const fn set_spdif0_clk_sel(&mut self, val: Spdif0ClkSel)
Selector for spdif0 clock multiplexer
Sourcepub const fn spdif0_clk_podf(&self) -> Spdif0ClkPodf
pub const fn spdif0_clk_podf(&self) -> Spdif0ClkPodf
Divider for spdif0 clock podf. Divider should be updated when output clock is gated.
Sourcepub const fn set_spdif0_clk_podf(&mut self, val: Spdif0ClkPodf)
pub const fn set_spdif0_clk_podf(&mut self, val: Spdif0ClkPodf)
Divider for spdif0 clock podf. Divider should be updated when output clock is gated.
Sourcepub const fn spdif0_clk_pred(&self) -> Spdif0ClkPred
pub const fn spdif0_clk_pred(&self) -> Spdif0ClkPred
Divider for spdif0 clock pred. Divider should be updated when output clock is gated.
Sourcepub const fn set_spdif0_clk_pred(&mut self, val: Spdif0ClkPred)
pub const fn set_spdif0_clk_pred(&mut self, val: Spdif0ClkPred)
Divider for spdif0 clock pred. Divider should be updated when output clock is gated.