#[repr(u8)]pub enum Fpl {
FPL_0 = 0,
FPL_1 = 1,
}Variants§
FPL_0 = 0
Engage PLL enable default way.
FPL_1 = 1
Engage PLL enable 3 CKIL clocks earlier at exiting low power mode (STOP). Should be used only if 24MHz OSC was active in low power mode.
Implementations§
Trait Implementations§
Source§impl Ord for Fpl
impl Ord for Fpl
Source§impl PartialOrd for Fpl
impl PartialOrd for Fpl
impl Copy for Fpl
impl Eq for Fpl
impl StructuralPartialEq for Fpl
Auto Trait Implementations§
impl Freeze for Fpl
impl RefUnwindSafe for Fpl
impl Send for Fpl
impl Sync for Fpl
impl Unpin for Fpl
impl UnwindSafe for Fpl
Blanket Implementations§
Source§impl<T> BorrowMut<T> for Twhere
T: ?Sized,
impl<T> BorrowMut<T> for Twhere
T: ?Sized,
Source§fn borrow_mut(&mut self) -> &mut T
fn borrow_mut(&mut self) -> &mut T
Mutably borrows from an owned value. Read more