#[repr(u8)]pub enum Tcsr2Tmode {
Show 16 variants
TMR_DIS = 0,
TMR_RE = 1,
TMR_FE = 2,
TMR_BE = 3,
TMR_OUT = 4,
TMR_TOGGLE = 5,
TMR_CLR = 6,
TMR_SET_OUT = 7,
_RESERVED_8 = 8,
TMR_CLR_SET1 = 9,
TMR_CLR_SET = 10,
_RESERVED_b = 11,
_RESERVED_c = 12,
_RESERVED_d = 13,
TMR_OUT_CMP_LOW = 14,
TMR_OUT_CMP_HIGH = 15,
}Variants§
TMR_DIS = 0
Timer Channel is disabled.
TMR_RE = 1
Timer Channel is configured for Input Capture on rising edge.
TMR_FE = 2
Timer Channel is configured for Input Capture on falling edge.
TMR_BE = 3
Timer Channel is configured for Input Capture on both edges.
TMR_OUT = 4
Timer Channel is configured for Output Compare - software only.
TMR_TOGGLE = 5
Timer Channel is configured for Output Compare - toggle output on compare.
TMR_CLR = 6
Timer Channel is configured for Output Compare - clear output on compare.
TMR_SET_OUT = 7
Timer Channel is configured for Output Compare - set output on compare.
_RESERVED_8 = 8
TMR_CLR_SET1 = 9
Timer Channel is configured for Output Compare - set output on compare, clear output on overflow.
TMR_CLR_SET = 10
Timer Channel is configured for Output Compare - clear output on compare, set output on overflow.
_RESERVED_b = 11
_RESERVED_c = 12
_RESERVED_d = 13
TMR_OUT_CMP_LOW = 14
Timer Channel is configured for Output Compare - pulse output low on compare for 1 to 32 1588-clock cycles as specified by TPWC.
TMR_OUT_CMP_HIGH = 15
Timer Channel is configured for Output Compare - pulse output high on compare for 1 to 32 1588-clock cycles as specified by TPWC.
Implementations§
Source§impl Tcsr2Tmode
impl Tcsr2Tmode
Trait Implementations§
Source§impl Clone for Tcsr2Tmode
impl Clone for Tcsr2Tmode
Source§fn clone(&self) -> Tcsr2Tmode
fn clone(&self) -> Tcsr2Tmode
1.0.0 · Source§fn clone_from(&mut self, source: &Self)
fn clone_from(&mut self, source: &Self)
source. Read more