Struct Flshcr2 

#[repr(transparent)]
pub struct Flshcr2(pub u32);

Flash Control Register 2

Tuple Fields

0: u32

Implementations

impl Flshcr2

pub const fn ardseqid(&self) -> u8

Sequence Index for AHB Read triggered Command in LUT.

pub const fn set_ardseqid(&mut self, val: u8)

Sequence Index for AHB Read triggered Command in LUT.

pub const fn ardseqnum(&self) -> u8

Sequence Number for AHB Read triggered Command in LUT.

pub const fn set_ardseqnum(&mut self, val: u8)

Sequence Number for AHB Read triggered Command in LUT.

pub const fn awrseqid(&self) -> u8

Sequence Index for AHB Write triggered Command.

pub const fn set_awrseqid(&mut self, val: u8)

Sequence Index for AHB Write triggered Command.

pub const fn awrseqnum(&self) -> u8

Sequence Number for AHB Write triggered Command.

pub const fn set_awrseqnum(&mut self, val: u8)

Sequence Number for AHB Write triggered Command.

pub const fn awrwait(&self) -> u16

For certain devices (such as FPGA), it need some time to write data into internal memory after the command sequences finished on FlexSPI interface. If another Read command sequence comes before previous programming finished internally, the read data may be wrong. This field is used to hold AHB Bus ready for AHB write access to wait the programming finished in external device. Then there will be no AHB read command triggered before the programming finished in external device. The Wait cycle between AHB triggered command sequences finished on FlexSPI interface and AHB return Bus ready: AWRWAIT * AWRWAITUNIT

pub const fn set_awrwait(&mut self, val: u16)

For certain devices (such as FPGA), it need some time to write data into internal memory after the command sequences finished on FlexSPI interface. If another Read command sequence comes before previous programming finished internally, the read data may be wrong. This field is used to hold AHB Bus ready for AHB write access to wait the programming finished in external device. Then there will be no AHB read command triggered before the programming finished in external device. The Wait cycle between AHB triggered command sequences finished on FlexSPI interface and AHB return Bus ready: AWRWAIT * AWRWAITUNIT

pub const fn awrwaitunit(&self) -> Awrwaitunit

AWRWAIT unit

pub const fn set_awrwaitunit(&mut self, val: Awrwaitunit)

AWRWAIT unit

pub const fn clrinstrptr(&self) -> bool

Clear the instruction pointer which is internally saved pointer by JMP_ON_CS.

pub const fn set_clrinstrptr(&mut self, val: bool)

Clear the instruction pointer which is internally saved pointer by JMP_ON_CS.

Trait Implementations

impl Clone for Flshcr2

fn clone(&self) -> Flshcr2

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for Flshcr2

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Default for Flshcr2

fn default() -> Flshcr2

Returns the “default value” for a type.

impl PartialEq for Flshcr2

fn eq(&self, other: &Flshcr2) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Flshcr2

impl Eq for Flshcr2

impl StructuralPartialEq for Flshcr2