#[repr(transparent)]pub struct Mcr2(pub u32);Expand description
Module Control Register 2
Tuple Fields§
§0: u32Implementations§
Source§impl Mcr2
impl Mcr2
Sourcepub const fn clrahbbufopt(&self) -> Clrahbbufopt
pub const fn clrahbbufopt(&self) -> Clrahbbufopt
Clear AHB buffer
Sourcepub const fn set_clrahbbufopt(&mut self, val: Clrahbbufopt)
pub const fn set_clrahbbufopt(&mut self, val: Clrahbbufopt)
Clear AHB buffer
Sourcepub const fn samedeviceen(&self) -> Samedeviceen
pub const fn samedeviceen(&self) -> Samedeviceen
All external devices are same devices (both in type and size) for A1/A2/B1/B2.
Sourcepub const fn set_samedeviceen(&mut self, val: Samedeviceen)
pub const fn set_samedeviceen(&mut self, val: Samedeviceen)
All external devices are same devices (both in type and size) for A1/A2/B1/B2.
Sourcepub const fn sckbdiffopt(&self) -> Sckbdiffopt
pub const fn sckbdiffopt(&self) -> Sckbdiffopt
B_SCLK pad can be used as A_SCLK differential clock output (inverted clock to A_SCLK). In this case, port B flash access is not available. After changing the value of this field, MCR0[SWRESET] should be set.
Sourcepub const fn set_sckbdiffopt(&mut self, val: Sckbdiffopt)
pub const fn set_sckbdiffopt(&mut self, val: Sckbdiffopt)
B_SCLK pad can be used as A_SCLK differential clock output (inverted clock to A_SCLK). In this case, port B flash access is not available. After changing the value of this field, MCR0[SWRESET] should be set.
Sourcepub const fn resumewait(&self) -> u8
pub const fn resumewait(&self) -> u8
Wait cycle (in AHB clock cycle) for idle state before suspended command sequence resumed.
Sourcepub const fn set_resumewait(&mut self, val: u8)
pub const fn set_resumewait(&mut self, val: u8)
Wait cycle (in AHB clock cycle) for idle state before suspended command sequence resumed.