Struct Iomuxc 

pub struct Iomuxc { /* private fields */ }

IOMUXC

Implementations

impl Iomuxc

pub const unsafe fn from_ptr(ptr: *mut ()) -> Self

pub const fn as_ptr(&self) -> *mut ()

pub const fn sw_mux_ctl_pad_gpio_emc_00(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_EMC_00 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_emc_01(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_EMC_01 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_emc_02(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_EMC_02 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_emc_03(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_EMC_03 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_emc_04(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_EMC_04 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_emc_05(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_EMC_05 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_emc_06(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_EMC_06 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_emc_07(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_EMC_07 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_emc_08(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_EMC_08 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_emc_09(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_EMC_09 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_emc_10(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_EMC_10 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_emc_11(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_EMC_11 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_emc_12(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_EMC_12 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_emc_13(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_EMC_13 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_emc_14(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_EMC_14 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_emc_15(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_EMC_15 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_emc_16(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_EMC_16 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_emc_17(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_EMC_17 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_emc_18(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_EMC_18 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_emc_19(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_EMC_19 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_emc_20(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_EMC_20 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_emc_21(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_EMC_21 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_emc_22(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_EMC_22 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_emc_23(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_EMC_23 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_emc_24(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_EMC_24 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_emc_25(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_EMC_25 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_emc_26(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_EMC_26 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_emc_27(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_EMC_27 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_emc_28(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_EMC_28 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_emc_29(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_EMC_29 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_emc_30(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_EMC_30 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_emc_31(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_EMC_31 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_emc_32(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_EMC_32 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_emc_33(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_EMC_33 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_emc_34(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_EMC_34 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_emc_35(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_EMC_35 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_emc_36(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_EMC_36 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_emc_37(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_EMC_37 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_emc_38(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_EMC_38 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_emc_39(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_EMC_39 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_emc_40(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_EMC_40 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_emc_41(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_EMC_41 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_ad_b0_00(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_AD_B0_00 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_ad_b0_01(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_AD_B0_01 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_ad_b0_02(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_AD_B0_02 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_ad_b0_03(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_AD_B0_03 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_ad_b0_04(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_AD_B0_04 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_ad_b0_05(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_AD_B0_05 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_ad_b0_06(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_AD_B0_06 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_ad_b0_07(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_AD_B0_07 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_ad_b0_08(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_AD_B0_08 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_ad_b0_09(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_AD_B0_09 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_ad_b0_10(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_AD_B0_10 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_ad_b0_11(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_AD_B0_11 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_ad_b0_12(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_AD_B0_12 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_ad_b0_13(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_AD_B0_13 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_ad_b0_14(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_AD_B0_14 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_ad_b0_15(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_AD_B0_15 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_ad_b1_00(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_AD_B1_00 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_ad_b1_01(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_AD_B1_01 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_ad_b1_02(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_AD_B1_02 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_ad_b1_03(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_AD_B1_03 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_ad_b1_04(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_AD_B1_04 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_ad_b1_05(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_AD_B1_05 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_ad_b1_06(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_AD_B1_06 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_ad_b1_07(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_AD_B1_07 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_ad_b1_08(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_AD_B1_08 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_ad_b1_09(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_AD_B1_09 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_ad_b1_10(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_AD_B1_10 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_ad_b1_11(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_AD_B1_11 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_ad_b1_12(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_AD_B1_12 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_ad_b1_13(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_AD_B1_13 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_ad_b1_14(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_AD_B1_14 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_ad_b1_15(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_AD_B1_15 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_b0_00(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_B0_00 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_b0_01(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_B0_01 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_b0_02(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_B0_02 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_b0_03(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_B0_03 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_b0_04(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_B0_04 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_b0_05(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_B0_05 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_b0_06(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_B0_06 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_b0_07(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_B0_07 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_b0_08(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_B0_08 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_b0_09(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_B0_09 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_b0_10(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_B0_10 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_b0_11(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_B0_11 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_b0_12(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_B0_12 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_b0_13(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_B0_13 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_b0_14(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_B0_14 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_b0_15(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_B0_15 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_b1_00(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_B1_00 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_b1_01(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_B1_01 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_b1_02(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_B1_02 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_b1_03(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_B1_03 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_b1_04(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_B1_04 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_b1_05(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_B1_05 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_b1_06(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_B1_06 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_b1_07(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_B1_07 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_b1_08(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_B1_08 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_b1_09(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_B1_09 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_b1_10(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_B1_10 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_b1_11(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_B1_11 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_b1_12(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_B1_12 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_b1_13(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_B1_13 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_b1_14(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_B1_14 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_b1_15(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_B1_15 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_sd_b0_00(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_SD_B0_00 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_sd_b0_01(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_SD_B0_01 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_sd_b0_02(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_SD_B0_02 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_sd_b0_03(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_SD_B0_03 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_sd_b0_04(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_SD_B0_04 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_sd_b0_05(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_SD_B0_05 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_sd_b1_00(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_SD_B1_00 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_sd_b1_01(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_SD_B1_01 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_sd_b1_02(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_SD_B1_02 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_sd_b1_03(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_SD_B1_03 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_sd_b1_04(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_SD_B1_04 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_sd_b1_05(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_SD_B1_05 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_sd_b1_06(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_SD_B1_06 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_sd_b1_07(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_SD_B1_07 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_sd_b1_08(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_SD_B1_08 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_sd_b1_09(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_SD_B1_09 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_sd_b1_10(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_SD_B1_10 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_sd_b1_11(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_SD_B1_11 SW MUX Control Register

pub const fn sw_pad_ctl_pad_gpio_emc_00(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_EMC_00 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_emc_01(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_EMC_01 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_emc_02(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_EMC_02 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_emc_03(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_EMC_03 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_emc_04(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_EMC_04 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_emc_05(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_EMC_05 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_emc_06(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_EMC_06 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_emc_07(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_EMC_07 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_emc_08(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_EMC_08 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_emc_09(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_EMC_09 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_emc_10(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_EMC_10 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_emc_11(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_EMC_11 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_emc_12(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_EMC_12 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_emc_13(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_EMC_13 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_emc_14(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_EMC_14 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_emc_15(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_EMC_15 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_emc_16(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_EMC_16 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_emc_17(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_EMC_17 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_emc_18(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_EMC_18 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_emc_19(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_EMC_19 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_emc_20(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_EMC_20 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_emc_21(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_EMC_21 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_emc_22(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_EMC_22 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_emc_23(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_EMC_23 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_emc_24(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_EMC_24 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_emc_25(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_EMC_25 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_emc_26(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_EMC_26 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_emc_27(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_EMC_27 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_emc_28(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_EMC_28 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_emc_29(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_EMC_29 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_emc_30(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_EMC_30 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_emc_31(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_EMC_31 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_emc_32(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_EMC_32 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_emc_33(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_EMC_33 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_emc_34(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_EMC_34 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_emc_35(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_EMC_35 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_emc_36(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_EMC_36 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_emc_37(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_EMC_37 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_emc_38(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_EMC_38 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_emc_39(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_EMC_39 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_emc_40(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_EMC_40 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_emc_41(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_EMC_41 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_ad_b0_00(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_AD_B0_00 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_ad_b0_01(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_AD_B0_01 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_ad_b0_02(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_AD_B0_02 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_ad_b0_03(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_AD_B0_03 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_ad_b0_04(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_AD_B0_04 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_ad_b0_05(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_AD_B0_05 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_ad_b0_06(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_AD_B0_06 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_ad_b0_07(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_AD_B0_07 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_ad_b0_08(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_AD_B0_08 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_ad_b0_09(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_AD_B0_09 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_ad_b0_10(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_AD_B0_10 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_ad_b0_11(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_AD_B0_11 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_ad_b0_12(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_AD_B0_12 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_ad_b0_13(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_AD_B0_13 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_ad_b0_14(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_AD_B0_14 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_ad_b0_15(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_AD_B0_15 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_ad_b1_00(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_AD_B1_00 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_ad_b1_01(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_AD_B1_01 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_ad_b1_02(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_AD_B1_02 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_ad_b1_03(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_AD_B1_03 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_ad_b1_04(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_AD_B1_04 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_ad_b1_05(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_AD_B1_05 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_ad_b1_06(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_AD_B1_06 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_ad_b1_07(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_AD_B1_07 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_ad_b1_08(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_AD_B1_08 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_ad_b1_09(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_AD_B1_09 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_ad_b1_10(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_AD_B1_10 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_ad_b1_11(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_AD_B1_11 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_ad_b1_12(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_AD_B1_12 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_ad_b1_13(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_AD_B1_13 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_ad_b1_14(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_AD_B1_14 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_ad_b1_15(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_AD_B1_15 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_b0_00(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_B0_00 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_b0_01(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_B0_01 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_b0_02(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_B0_02 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_b0_03(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_B0_03 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_b0_04(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_B0_04 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_b0_05(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_B0_05 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_b0_06(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_B0_06 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_b0_07(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_B0_07 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_b0_08(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_B0_08 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_b0_09(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_B0_09 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_b0_10(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_B0_10 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_b0_11(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_B0_11 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_b0_12(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_B0_12 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_b0_13(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_B0_13 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_b0_14(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_B0_14 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_b0_15(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_B0_15 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_b1_00(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_B1_00 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_b1_01(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_B1_01 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_b1_02(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_B1_02 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_b1_03(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_B1_03 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_b1_04(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_B1_04 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_b1_05(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_B1_05 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_b1_06(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_B1_06 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_b1_07(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_B1_07 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_b1_08(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_B1_08 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_b1_09(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_B1_09 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_b1_10(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_B1_10 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_b1_11(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_B1_11 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_b1_12(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_B1_12 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_b1_13(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_B1_13 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_b1_14(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_B1_14 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_b1_15(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_B1_15 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_sd_b0_00(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_SD_B0_00 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_sd_b0_01(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_SD_B0_01 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_sd_b0_02(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_SD_B0_02 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_sd_b0_03(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_SD_B0_03 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_sd_b0_04(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_SD_B0_04 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_sd_b0_05(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_SD_B0_05 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_sd_b1_00(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_SD_B1_00 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_sd_b1_01(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_SD_B1_01 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_sd_b1_02(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_SD_B1_02 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_sd_b1_03(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_SD_B1_03 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_sd_b1_04(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_SD_B1_04 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_sd_b1_05(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_SD_B1_05 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_sd_b1_06(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_SD_B1_06 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_sd_b1_07(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_SD_B1_07 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_sd_b1_08(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_SD_B1_08 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_sd_b1_09(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_SD_B1_09 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_sd_b1_10(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_SD_B1_10 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_sd_b1_11(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_SD_B1_11 SW PAD Control Register

pub const fn anatop_usb_otg1_id_select_input( self, ) -> Reg<AnatopUsbOtg1IdSelectInput, RW>

ANATOP_USB_OTG1_ID_SELECT_INPUT DAISY Register

pub const fn anatop_usb_otg2_id_select_input( self, ) -> Reg<AnatopUsbOtg2IdSelectInput, RW>

ANATOP_USB_OTG2_ID_SELECT_INPUT DAISY Register

pub const fn ccm_pmic_ready_select_input( self, ) -> Reg<CcmPmicReadySelectInput, RW>

CCM_PMIC_READY_SELECT_INPUT DAISY Register

pub const fn csi_data02_select_input(self) -> Reg<CsiData02SelectInput, RW>

CSI_DATA02_SELECT_INPUT DAISY Register

pub const fn csi_data03_select_input(self) -> Reg<CsiData03SelectInput, RW>

CSI_DATA03_SELECT_INPUT DAISY Register

pub const fn csi_data04_select_input(self) -> Reg<CsiData04SelectInput, RW>

CSI_DATA04_SELECT_INPUT DAISY Register

pub const fn csi_data05_select_input(self) -> Reg<CsiData05SelectInput, RW>

CSI_DATA05_SELECT_INPUT DAISY Register

pub const fn csi_data06_select_input(self) -> Reg<CsiData06SelectInput, RW>

CSI_DATA06_SELECT_INPUT DAISY Register

pub const fn csi_data07_select_input(self) -> Reg<CsiData07SelectInput, RW>

CSI_DATA07_SELECT_INPUT DAISY Register

pub const fn csi_data08_select_input(self) -> Reg<CsiData08SelectInput, RW>

CSI_DATA08_SELECT_INPUT DAISY Register

pub const fn csi_data09_select_input(self) -> Reg<CsiData09SelectInput, RW>

CSI_DATA09_SELECT_INPUT DAISY Register

pub const fn csi_hsync_select_input(self) -> Reg<CsiHsyncSelectInput, RW>

CSI_HSYNC_SELECT_INPUT DAISY Register

pub const fn csi_pixclk_select_input(self) -> Reg<CsiPixclkSelectInput, RW>

CSI_PIXCLK_SELECT_INPUT DAISY Register

pub const fn csi_vsync_select_input(self) -> Reg<CsiVsyncSelectInput, RW>

CSI_VSYNC_SELECT_INPUT DAISY Register

pub const fn enet_ipg_clk_rmii_select_input( self, ) -> Reg<EnetIpgClkRmiiSelectInput, RW>

ENET_IPG_CLK_RMII_SELECT_INPUT DAISY Register

pub const fn enet_mdio_select_input(self) -> Reg<EnetMdioSelectInput, RW>

ENET_MDIO_SELECT_INPUT DAISY Register

pub const fn enet0_rxdata_select_input(self) -> Reg<Enet0RxdataSelectInput, RW>

ENET0_RXDATA_SELECT_INPUT DAISY Register

pub const fn enet1_rxdata_select_input(self) -> Reg<Enet1RxdataSelectInput, RW>

ENET1_RXDATA_SELECT_INPUT DAISY Register

pub const fn enet_rxen_select_input(self) -> Reg<EnetRxenSelectInput, RW>

ENET_RXEN_SELECT_INPUT DAISY Register

pub const fn enet_rxerr_select_input(self) -> Reg<EnetRxerrSelectInput, RW>

ENET_RXERR_SELECT_INPUT DAISY Register

pub const fn enet0_timer_select_input(self) -> Reg<Enet0TimerSelectInput, RW>

ENET0_TIMER_SELECT_INPUT DAISY Register

pub const fn enet_txclk_select_input(self) -> Reg<EnetTxclkSelectInput, RW>

ENET_TXCLK_SELECT_INPUT DAISY Register

pub const fn flexcan1_rx_select_input(self) -> Reg<Flexcan1RxSelectInput, RW>

FLEXCAN1_RX_SELECT_INPUT DAISY Register

pub const fn flexcan2_rx_select_input(self) -> Reg<Flexcan2RxSelectInput, RW>

FLEXCAN2_RX_SELECT_INPUT DAISY Register

pub const fn flexpwm1_pwma3_select_input( self, ) -> Reg<Flexpwm1Pwma3SelectInput, RW>

FLEXPWM1_PWMA3_SELECT_INPUT DAISY Register

pub const fn flexpwm1_pwma0_select_input( self, ) -> Reg<Flexpwm1Pwma0SelectInput, RW>

FLEXPWM1_PWMA0_SELECT_INPUT DAISY Register

pub const fn flexpwm1_pwma1_select_input( self, ) -> Reg<Flexpwm1Pwma1SelectInput, RW>

FLEXPWM1_PWMA1_SELECT_INPUT DAISY Register

pub const fn flexpwm1_pwma2_select_input( self, ) -> Reg<Flexpwm1Pwma2SelectInput, RW>

FLEXPWM1_PWMA2_SELECT_INPUT DAISY Register

pub const fn flexpwm1_pwmb3_select_input( self, ) -> Reg<Flexpwm1Pwmb3SelectInput, RW>

FLEXPWM1_PWMB3_SELECT_INPUT DAISY Register

pub const fn flexpwm1_pwmb0_select_input( self, ) -> Reg<Flexpwm1Pwmb0SelectInput, RW>

FLEXPWM1_PWMB0_SELECT_INPUT DAISY Register

pub const fn flexpwm1_pwmb1_select_input( self, ) -> Reg<Flexpwm1Pwmb1SelectInput, RW>

FLEXPWM1_PWMB1_SELECT_INPUT DAISY Register

pub const fn flexpwm1_pwmb2_select_input( self, ) -> Reg<Flexpwm1Pwmb2SelectInput, RW>

FLEXPWM1_PWMB2_SELECT_INPUT DAISY Register

pub const fn flexpwm2_pwma3_select_input( self, ) -> Reg<Flexpwm2Pwma3SelectInput, RW>

FLEXPWM2_PWMA3_SELECT_INPUT DAISY Register

pub const fn flexpwm2_pwma0_select_input( self, ) -> Reg<Flexpwm2Pwma0SelectInput, RW>

FLEXPWM2_PWMA0_SELECT_INPUT DAISY Register

pub const fn flexpwm2_pwma1_select_input( self, ) -> Reg<Flexpwm2Pwma1SelectInput, RW>

FLEXPWM2_PWMA1_SELECT_INPUT DAISY Register

pub const fn flexpwm2_pwma2_select_input( self, ) -> Reg<Flexpwm2Pwma2SelectInput, RW>

FLEXPWM2_PWMA2_SELECT_INPUT DAISY Register

pub const fn flexpwm2_pwmb3_select_input( self, ) -> Reg<Flexpwm2Pwmb3SelectInput, RW>

FLEXPWM2_PWMB3_SELECT_INPUT DAISY Register

pub const fn flexpwm2_pwmb0_select_input( self, ) -> Reg<Flexpwm2Pwmb0SelectInput, RW>

FLEXPWM2_PWMB0_SELECT_INPUT DAISY Register

pub const fn flexpwm2_pwmb1_select_input( self, ) -> Reg<Flexpwm2Pwmb1SelectInput, RW>

FLEXPWM2_PWMB1_SELECT_INPUT DAISY Register

pub const fn flexpwm2_pwmb2_select_input( self, ) -> Reg<Flexpwm2Pwmb2SelectInput, RW>

FLEXPWM2_PWMB2_SELECT_INPUT DAISY Register

pub const fn flexpwm4_pwma0_select_input( self, ) -> Reg<Flexpwm4Pwma0SelectInput, RW>

FLEXPWM4_PWMA0_SELECT_INPUT DAISY Register

pub const fn flexpwm4_pwma1_select_input( self, ) -> Reg<Flexpwm4Pwma1SelectInput, RW>

FLEXPWM4_PWMA1_SELECT_INPUT DAISY Register

pub const fn flexpwm4_pwma2_select_input( self, ) -> Reg<Flexpwm4Pwma2SelectInput, RW>

FLEXPWM4_PWMA2_SELECT_INPUT DAISY Register

pub const fn flexpwm4_pwma3_select_input( self, ) -> Reg<Flexpwm4Pwma3SelectInput, RW>

FLEXPWM4_PWMA3_SELECT_INPUT DAISY Register

pub const fn flexspia_dqs_select_input(self) -> Reg<FlexspiaDqsSelectInput, RW>

FLEXSPIA_DQS_SELECT_INPUT DAISY Register

pub const fn flexspia_data0_select_input( self, ) -> Reg<FlexspiaData0SelectInput, RW>

FLEXSPIA_DATA0_SELECT_INPUT DAISY Register

pub const fn flexspia_data1_select_input( self, ) -> Reg<FlexspiaData1SelectInput, RW>

FLEXSPIA_DATA1_SELECT_INPUT DAISY Register

pub const fn flexspia_data2_select_input( self, ) -> Reg<FlexspiaData2SelectInput, RW>

FLEXSPIA_DATA2_SELECT_INPUT DAISY Register

pub const fn flexspia_data3_select_input( self, ) -> Reg<FlexspiaData3SelectInput, RW>

FLEXSPIA_DATA3_SELECT_INPUT DAISY Register

pub const fn flexspib_data0_select_input( self, ) -> Reg<FlexspibData0SelectInput, RW>

FLEXSPIB_DATA0_SELECT_INPUT DAISY Register

pub const fn flexspib_data1_select_input( self, ) -> Reg<FlexspibData1SelectInput, RW>

FLEXSPIB_DATA1_SELECT_INPUT DAISY Register

pub const fn flexspib_data2_select_input( self, ) -> Reg<FlexspibData2SelectInput, RW>

FLEXSPIB_DATA2_SELECT_INPUT DAISY Register

pub const fn flexspib_data3_select_input( self, ) -> Reg<FlexspibData3SelectInput, RW>

FLEXSPIB_DATA3_SELECT_INPUT DAISY Register

pub const fn flexspia_sck_select_input(self) -> Reg<FlexspiaSckSelectInput, RW>

FLEXSPIA_SCK_SELECT_INPUT DAISY Register

pub const fn lpi2c1_scl_select_input(self) -> Reg<Lpi2c1SclSelectInput, RW>

LPI2C1_SCL_SELECT_INPUT DAISY Register

pub const fn lpi2c1_sda_select_input(self) -> Reg<Lpi2c1SdaSelectInput, RW>

LPI2C1_SDA_SELECT_INPUT DAISY Register

pub const fn lpi2c2_scl_select_input(self) -> Reg<Lpi2c2SclSelectInput, RW>

LPI2C2_SCL_SELECT_INPUT DAISY Register

pub const fn lpi2c2_sda_select_input(self) -> Reg<Lpi2c2SdaSelectInput, RW>

LPI2C2_SDA_SELECT_INPUT DAISY Register

pub const fn lpi2c3_scl_select_input(self) -> Reg<Lpi2c3SclSelectInput, RW>

LPI2C3_SCL_SELECT_INPUT DAISY Register

pub const fn lpi2c3_sda_select_input(self) -> Reg<Lpi2c3SdaSelectInput, RW>

LPI2C3_SDA_SELECT_INPUT DAISY Register

pub const fn lpi2c4_scl_select_input(self) -> Reg<Lpi2c4SclSelectInput, RW>

LPI2C4_SCL_SELECT_INPUT DAISY Register

pub const fn lpi2c4_sda_select_input(self) -> Reg<Lpi2c4SdaSelectInput, RW>

LPI2C4_SDA_SELECT_INPUT DAISY Register

pub const fn lpspi1_pcs0_select_input(self) -> Reg<Lpspi1Pcs0SelectInput, RW>

LPSPI1_PCS0_SELECT_INPUT DAISY Register

pub const fn lpspi1_sck_select_input(self) -> Reg<Lpspi1SckSelectInput, RW>

LPSPI1_SCK_SELECT_INPUT DAISY Register

pub const fn lpspi1_sdi_select_input(self) -> Reg<Lpspi1SdiSelectInput, RW>

LPSPI1_SDI_SELECT_INPUT DAISY Register

pub const fn lpspi1_sdo_select_input(self) -> Reg<Lpspi1SdoSelectInput, RW>

LPSPI1_SDO_SELECT_INPUT DAISY Register

pub const fn lpspi2_pcs0_select_input(self) -> Reg<Lpspi2Pcs0SelectInput, RW>

LPSPI2_PCS0_SELECT_INPUT DAISY Register

pub const fn lpspi2_sck_select_input(self) -> Reg<Lpspi2SckSelectInput, RW>

LPSPI2_SCK_SELECT_INPUT DAISY Register

pub const fn lpspi2_sdi_select_input(self) -> Reg<Lpspi2SdiSelectInput, RW>

LPSPI2_SDI_SELECT_INPUT DAISY Register

pub const fn lpspi2_sdo_select_input(self) -> Reg<Lpspi2SdoSelectInput, RW>

LPSPI2_SDO_SELECT_INPUT DAISY Register

pub const fn lpspi3_pcs0_select_input(self) -> Reg<Lpspi3Pcs0SelectInput, RW>

LPSPI3_PCS0_SELECT_INPUT DAISY Register

pub const fn lpspi3_sck_select_input(self) -> Reg<Lpspi3SckSelectInput, RW>

LPSPI3_SCK_SELECT_INPUT DAISY Register

pub const fn lpspi3_sdi_select_input(self) -> Reg<Lpspi3SdiSelectInput, RW>

LPSPI3_SDI_SELECT_INPUT DAISY Register

pub const fn lpspi3_sdo_select_input(self) -> Reg<Lpspi3SdoSelectInput, RW>

LPSPI3_SDO_SELECT_INPUT DAISY Register

pub const fn lpspi4_pcs0_select_input(self) -> Reg<Lpspi4Pcs0SelectInput, RW>

LPSPI4_PCS0_SELECT_INPUT DAISY Register

pub const fn lpspi4_sck_select_input(self) -> Reg<Lpspi4SckSelectInput, RW>

LPSPI4_SCK_SELECT_INPUT DAISY Register

pub const fn lpspi4_sdi_select_input(self) -> Reg<Lpspi4SdiSelectInput, RW>

LPSPI4_SDI_SELECT_INPUT DAISY Register

pub const fn lpspi4_sdo_select_input(self) -> Reg<Lpspi4SdoSelectInput, RW>

LPSPI4_SDO_SELECT_INPUT DAISY Register

pub const fn lpuart2_rx_select_input(self) -> Reg<Lpuart2RxSelectInput, RW>

LPUART2_RX_SELECT_INPUT DAISY Register

pub const fn lpuart2_tx_select_input(self) -> Reg<Lpuart2TxSelectInput, RW>

LPUART2_TX_SELECT_INPUT DAISY Register

pub const fn lpuart3_cts_b_select_input(self) -> Reg<Lpuart3CtsBSelectInput, RW>

LPUART3_CTS_B_SELECT_INPUT DAISY Register

pub const fn lpuart3_rx_select_input(self) -> Reg<Lpuart3RxSelectInput, RW>

LPUART3_RX_SELECT_INPUT DAISY Register

pub const fn lpuart3_tx_select_input(self) -> Reg<Lpuart3TxSelectInput, RW>

LPUART3_TX_SELECT_INPUT DAISY Register

pub const fn lpuart4_rx_select_input(self) -> Reg<Lpuart4RxSelectInput, RW>

LPUART4_RX_SELECT_INPUT DAISY Register

pub const fn lpuart4_tx_select_input(self) -> Reg<Lpuart4TxSelectInput, RW>

LPUART4_TX_SELECT_INPUT DAISY Register

pub const fn lpuart5_rx_select_input(self) -> Reg<Lpuart5RxSelectInput, RW>

LPUART5_RX_SELECT_INPUT DAISY Register

pub const fn lpuart5_tx_select_input(self) -> Reg<Lpuart5TxSelectInput, RW>

LPUART5_TX_SELECT_INPUT DAISY Register

pub const fn lpuart6_rx_select_input(self) -> Reg<Lpuart6RxSelectInput, RW>

LPUART6_RX_SELECT_INPUT DAISY Register

pub const fn lpuart6_tx_select_input(self) -> Reg<Lpuart6TxSelectInput, RW>

LPUART6_TX_SELECT_INPUT DAISY Register

pub const fn lpuart7_rx_select_input(self) -> Reg<Lpuart7RxSelectInput, RW>

LPUART7_RX_SELECT_INPUT DAISY Register

pub const fn lpuart7_tx_select_input(self) -> Reg<Lpuart7TxSelectInput, RW>

LPUART7_TX_SELECT_INPUT DAISY Register

pub const fn lpuart8_rx_select_input(self) -> Reg<Lpuart8RxSelectInput, RW>

LPUART8_RX_SELECT_INPUT DAISY Register

pub const fn lpuart8_tx_select_input(self) -> Reg<Lpuart8TxSelectInput, RW>

LPUART8_TX_SELECT_INPUT DAISY Register

pub const fn nmi_select_input(self) -> Reg<NmiSelectInput, RW>

NMI_GLUE_NMI_SELECT_INPUT DAISY Register

pub const fn qtimer2_timer0_select_input( self, ) -> Reg<Qtimer2Timer0SelectInput, RW>

QTIMER2_TIMER0_SELECT_INPUT DAISY Register

pub const fn qtimer2_timer1_select_input( self, ) -> Reg<Qtimer2Timer1SelectInput, RW>

QTIMER2_TIMER1_SELECT_INPUT DAISY Register

pub const fn qtimer2_timer2_select_input( self, ) -> Reg<Qtimer2Timer2SelectInput, RW>

QTIMER2_TIMER2_SELECT_INPUT DAISY Register

pub const fn qtimer2_timer3_select_input( self, ) -> Reg<Qtimer2Timer3SelectInput, RW>

QTIMER2_TIMER3_SELECT_INPUT DAISY Register

pub const fn qtimer3_timer0_select_input( self, ) -> Reg<Qtimer3Timer0SelectInput, RW>

QTIMER3_TIMER0_SELECT_INPUT DAISY Register

pub const fn qtimer3_timer1_select_input( self, ) -> Reg<Qtimer3Timer1SelectInput, RW>

QTIMER3_TIMER1_SELECT_INPUT DAISY Register

pub const fn qtimer3_timer2_select_input( self, ) -> Reg<Qtimer3Timer2SelectInput, RW>

QTIMER3_TIMER2_SELECT_INPUT DAISY Register

pub const fn qtimer3_timer3_select_input( self, ) -> Reg<Qtimer3Timer3SelectInput, RW>

QTIMER3_TIMER3_SELECT_INPUT DAISY Register

pub const fn sai1_mclk2_select_input(self) -> Reg<Sai1Mclk2SelectInput, RW>

SAI1_MCLK2_SELECT_INPUT DAISY Register

pub const fn sai1_rx_bclk_select_input(self) -> Reg<Sai1RxBclkSelectInput, RW>

SAI1_RX_BCLK_SELECT_INPUT DAISY Register

pub const fn sai1_rx_data0_select_input(self) -> Reg<Sai1RxData0SelectInput, RW>

SAI1_RX_DATA0_SELECT_INPUT DAISY Register

pub const fn sai1_rx_data1_select_input(self) -> Reg<Sai1RxData1SelectInput, RW>

SAI1_RX_DATA1_SELECT_INPUT DAISY Register

pub const fn sai1_rx_data2_select_input(self) -> Reg<Sai1RxData2SelectInput, RW>

SAI1_RX_DATA2_SELECT_INPUT DAISY Register

pub const fn sai1_rx_data3_select_input(self) -> Reg<Sai1RxData3SelectInput, RW>

SAI1_RX_DATA3_SELECT_INPUT DAISY Register

pub const fn sai1_rx_sync_select_input(self) -> Reg<Sai1RxSyncSelectInput, RW>

SAI1_RX_SYNC_SELECT_INPUT DAISY Register

pub const fn sai1_tx_bclk_select_input(self) -> Reg<Sai1TxBclkSelectInput, RW>

SAI1_TX_BCLK_SELECT_INPUT DAISY Register

pub const fn sai1_tx_sync_select_input(self) -> Reg<Sai1TxSyncSelectInput, RW>

SAI1_TX_SYNC_SELECT_INPUT DAISY Register

pub const fn sai2_mclk2_select_input(self) -> Reg<Sai2Mclk2SelectInput, RW>

SAI2_MCLK2_SELECT_INPUT DAISY Register

pub const fn sai2_rx_bclk_select_input(self) -> Reg<Sai2RxBclkSelectInput, RW>

SAI2_RX_BCLK_SELECT_INPUT DAISY Register

pub const fn sai2_rx_data0_select_input(self) -> Reg<Sai2RxData0SelectInput, RW>

SAI2_RX_DATA0_SELECT_INPUT DAISY Register

pub const fn sai2_rx_sync_select_input(self) -> Reg<Sai2RxSyncSelectInput, RW>

SAI2_RX_SYNC_SELECT_INPUT DAISY Register

pub const fn sai2_tx_bclk_select_input(self) -> Reg<Sai2TxBclkSelectInput, RW>

SAI2_TX_BCLK_SELECT_INPUT DAISY Register

pub const fn sai2_tx_sync_select_input(self) -> Reg<Sai2TxSyncSelectInput, RW>

SAI2_TX_SYNC_SELECT_INPUT DAISY Register

pub const fn spdif_in_select_input(self) -> Reg<SpdifInSelectInput, RW>

SPDIF_IN_SELECT_INPUT DAISY Register

pub const fn usb_otg2_oc_select_input(self) -> Reg<UsbOtg2OcSelectInput, RW>

USB_OTG2_OC_SELECT_INPUT DAISY Register

pub const fn usb_otg1_oc_select_input(self) -> Reg<UsbOtg1OcSelectInput, RW>

USB_OTG1_OC_SELECT_INPUT DAISY Register

pub const fn usdhc1_cd_b_select_input(self) -> Reg<Usdhc1CdBSelectInput, RW>

USDHC1_CD_B_SELECT_INPUT DAISY Register

pub const fn usdhc1_wp_select_input(self) -> Reg<Usdhc1WpSelectInput, RW>

USDHC1_WP_SELECT_INPUT DAISY Register

pub const fn usdhc2_clk_select_input(self) -> Reg<Usdhc2ClkSelectInput, RW>

USDHC2_CLK_SELECT_INPUT DAISY Register

pub const fn usdhc2_cd_b_select_input(self) -> Reg<Usdhc2CdBSelectInput, RW>

USDHC2_CD_B_SELECT_INPUT DAISY Register

pub const fn usdhc2_cmd_select_input(self) -> Reg<Usdhc2CmdSelectInput, RW>

USDHC2_CMD_SELECT_INPUT DAISY Register

pub const fn usdhc2_data0_select_input(self) -> Reg<Usdhc2Data0SelectInput, RW>

USDHC2_DATA0_SELECT_INPUT DAISY Register

pub const fn usdhc2_data1_select_input(self) -> Reg<Usdhc2Data1SelectInput, RW>

USDHC2_DATA1_SELECT_INPUT DAISY Register

pub const fn usdhc2_data2_select_input(self) -> Reg<Usdhc2Data2SelectInput, RW>

USDHC2_DATA2_SELECT_INPUT DAISY Register

pub const fn usdhc2_data3_select_input(self) -> Reg<Usdhc2Data3SelectInput, RW>

USDHC2_DATA3_SELECT_INPUT DAISY Register

pub const fn usdhc2_data4_select_input(self) -> Reg<Usdhc2Data4SelectInput, RW>

USDHC2_DATA4_SELECT_INPUT DAISY Register

pub const fn usdhc2_data5_select_input(self) -> Reg<Usdhc2Data5SelectInput, RW>

USDHC2_DATA5_SELECT_INPUT DAISY Register

pub const fn usdhc2_data6_select_input(self) -> Reg<Usdhc2Data6SelectInput, RW>

USDHC2_DATA6_SELECT_INPUT DAISY Register

pub const fn usdhc2_data7_select_input(self) -> Reg<Usdhc2Data7SelectInput, RW>

USDHC2_DATA7_SELECT_INPUT DAISY Register

pub const fn usdhc2_wp_select_input(self) -> Reg<Usdhc2WpSelectInput, RW>

USDHC2_WP_SELECT_INPUT DAISY Register

pub const fn xbar1_in02_select_input(self) -> Reg<Xbar1In02SelectInput, RW>

XBAR1_IN02_SELECT_INPUT DAISY Register

pub const fn xbar1_in03_select_input(self) -> Reg<Xbar1In03SelectInput, RW>

XBAR1_IN03_SELECT_INPUT DAISY Register

pub const fn xbar1_in04_select_input(self) -> Reg<Xbar1In04SelectInput, RW>

XBAR1_IN04_SELECT_INPUT DAISY Register

pub const fn xbar1_in05_select_input(self) -> Reg<Xbar1In05SelectInput, RW>

XBAR1_IN05_SELECT_INPUT DAISY Register

pub const fn xbar1_in06_select_input(self) -> Reg<Xbar1In06SelectInput, RW>

XBAR1_IN06_SELECT_INPUT DAISY Register

pub const fn xbar1_in07_select_input(self) -> Reg<Xbar1In07SelectInput, RW>

XBAR1_IN07_SELECT_INPUT DAISY Register

pub const fn xbar1_in08_select_input(self) -> Reg<Xbar1In08SelectInput, RW>

XBAR1_IN08_SELECT_INPUT DAISY Register

pub const fn xbar1_in09_select_input(self) -> Reg<Xbar1In09SelectInput, RW>

XBAR1_IN09_SELECT_INPUT DAISY Register

pub const fn xbar1_in17_select_input(self) -> Reg<Xbar1In17SelectInput, RW>

XBAR1_IN17_SELECT_INPUT DAISY Register

pub const fn xbar1_in18_select_input(self) -> Reg<Xbar1In18SelectInput, RW>

XBAR1_IN18_SELECT_INPUT DAISY Register

pub const fn xbar1_in20_select_input(self) -> Reg<Xbar1In20SelectInput, RW>

XBAR1_IN20_SELECT_INPUT DAISY Register

pub const fn xbar1_in22_select_input(self) -> Reg<Xbar1In22SelectInput, RW>

XBAR1_IN22_SELECT_INPUT DAISY Register

pub const fn xbar1_in23_select_input(self) -> Reg<Xbar1In23SelectInput, RW>

XBAR1_IN23_SELECT_INPUT DAISY Register

pub const fn xbar1_in24_select_input(self) -> Reg<Xbar1In24SelectInput, RW>

XBAR1_IN24_SELECT_INPUT DAISY Register

pub const fn xbar1_in14_select_input(self) -> Reg<Xbar1In14SelectInput, RW>

XBAR1_IN14_SELECT_INPUT DAISY Register

pub const fn xbar1_in15_select_input(self) -> Reg<Xbar1In15SelectInput, RW>

XBAR1_IN15_SELECT_INPUT DAISY Register

pub const fn xbar1_in16_select_input(self) -> Reg<Xbar1In16SelectInput, RW>

XBAR1_IN16_SELECT_INPUT DAISY Register

pub const fn xbar1_in25_select_input(self) -> Reg<Xbar1In25SelectInput, RW>

XBAR1_IN25_SELECT_INPUT DAISY Register

pub const fn xbar1_in19_select_input(self) -> Reg<Xbar1In19SelectInput, RW>

XBAR1_IN19_SELECT_INPUT DAISY Register

pub const fn xbar1_in21_select_input(self) -> Reg<Xbar1In21SelectInput, RW>

XBAR1_IN23_SELECT_INPUT DAISY Register

pub const fn sw_mux_ctl_pad_gpio_spi_b0_00(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_SPI_B0_00 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_spi_b0_01(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_SPI_B0_01 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_spi_b0_02(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_SPI_B0_02 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_spi_b0_03(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_SPI_B0_03 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_spi_b0_04(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_SPI_B0_04 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_spi_b0_05(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_SPI_B0_05 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_spi_b0_06(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_SPI_B0_06 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_spi_b0_07(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_SPI_B0_07 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_spi_b0_08(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_SPI_B0_08 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_spi_b0_09(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_SPI_B0_09 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_spi_b0_10(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_SPI_B0_10 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_spi_b0_11(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_SPI_B0_11 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_spi_b0_12(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_SPI_B0_12 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_spi_b0_13(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_SPI_B0_13 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_spi_b1_00(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_SPI_B1_00 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_spi_b1_01(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_SPI_B1_01 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_spi_b1_02(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_SPI_B1_02 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_spi_b1_03(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_SPI_B1_03 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_spi_b1_04(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_SPI_B1_04 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_spi_b1_05(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_SPI_B1_05 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_spi_b1_06(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_SPI_B1_06 SW MUX Control Register

pub const fn sw_mux_ctl_pad_gpio_spi_b1_07(self) -> Reg<MuxCtl, RW>

SW_MUX_CTL_PAD_GPIO_SPI_B1_07 SW MUX Control Register

pub const fn sw_pad_ctl_pad_gpio_spi_b0_00(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_SPI_B0_00 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_spi_b0_01(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_SPI_B0_01 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_spi_b0_02(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_SPI_B0_02 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_spi_b0_03(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_SPI_B0_03 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_spi_b0_04(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_SPI_B0_04 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_spi_b0_05(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_SPI_B0_05 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_spi_b0_06(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_SPI_B0_06 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_spi_b0_07(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_SPI_B0_07 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_spi_b0_08(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_SPI_B0_08 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_spi_b0_09(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_SPI_B0_09 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_spi_b0_10(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_SPI_B0_10 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_spi_b0_11(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_SPI_B0_11 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_spi_b0_12(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_SPI_B0_12 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_spi_b0_13(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_SPI_B0_13 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_spi_b1_00(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_SPI_B1_00 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_spi_b1_01(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_SPI_B1_01 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_spi_b1_02(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_SPI_B1_02 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_spi_b1_03(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_SPI_B1_03 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_spi_b1_04(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_SPI_B1_04 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_spi_b1_05(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_SPI_B1_05 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_spi_b1_06(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_SPI_B1_06 SW PAD Control Register

pub const fn sw_pad_ctl_pad_gpio_spi_b1_07(self) -> Reg<Ctl, RW>

SW_PAD_CTL_PAD_GPIO_SPI_B1_07 SW PAD Control Register

pub const fn enet2_ipg_clk_rmii_select_input( self, ) -> Reg<Enet2IpgClkRmiiSelectInput, RW>

ENET2_IPG_CLK_RMII_SELECT_INPUT DAISY Register

pub const fn enet2_ipp_ind_mac0_mdio_select_input( self, ) -> Reg<Enet2IppIndMac0MdioSelectInput, RW>

ENET2_IPP_IND_MAC0_MDIO_SELECT_INPUT DAISY Register

pub const fn enet2_ipp_ind_mac0_rxdata_select_input_0( self, ) -> Reg<Enet2IppIndMac0RxdataSelectInput0, RW>

ENET2_IPP_IND_MAC0_RXDATA_SELECT_INPUT_0 DAISY Register

pub const fn enet2_ipp_ind_mac0_rxdata_select_input_1( self, ) -> Reg<Enet2IppIndMac0RxdataSelectInput1, RW>

ENET2_IPP_IND_MAC0_RXDATA_SELECT_INPUT_1 DAISY Register

pub const fn enet2_ipp_ind_mac0_rxen_select_input( self, ) -> Reg<Enet2IppIndMac0RxenSelectInput, RW>

ENET2_IPP_IND_MAC0_RXEN_SELECT_INPUT DAISY Register

pub const fn enet2_ipp_ind_mac0_rxerr_select_input( self, ) -> Reg<Enet2IppIndMac0RxerrSelectInput, RW>

ENET2_IPP_IND_MAC0_RXERR_SELECT_INPUT DAISY Register

pub const fn enet2_ipp_ind_mac0_timer_select_input_0( self, ) -> Reg<Enet2IppIndMac0TimerSelectInput0, RW>

ENET2_IPP_IND_MAC0_TIMER_SELECT_INPUT_0 DAISY Register

pub const fn enet2_ipp_ind_mac0_txclk_select_input( self, ) -> Reg<Enet2IppIndMac0TxclkSelectInput, RW>

ENET2_IPP_IND_MAC0_TXCLK_SELECT_INPUT DAISY Register

pub const fn flexspi2_ipp_ind_dqs_fa_select_input( self, ) -> Reg<Flexspi2IppIndDqsFaSelectInput, RW>

FLEXSPI2_IPP_IND_DQS_FA_SELECT_INPUT DAISY Register

pub const fn flexspi2_ipp_ind_io_fa_bit0_select_input( self, ) -> Reg<Flexspi2IppIndIoFaBit0SelectInput, RW>

FLEXSPI2_IPP_IND_IO_FA_BIT0_SELECT_INPUT DAISY Register

pub const fn flexspi2_ipp_ind_io_fa_bit1_select_input( self, ) -> Reg<Flexspi2IppIndIoFaBit1SelectInput, RW>

FLEXSPI2_IPP_IND_IO_FA_BIT1_SELECT_INPUT DAISY Register

pub const fn flexspi2_ipp_ind_io_fa_bit2_select_input( self, ) -> Reg<Flexspi2IppIndIoFaBit2SelectInput, RW>

FLEXSPI2_IPP_IND_IO_FA_BIT2_SELECT_INPUT DAISY Register

pub const fn flexspi2_ipp_ind_io_fa_bit3_select_input( self, ) -> Reg<Flexspi2IppIndIoFaBit3SelectInput, RW>

FLEXSPI2_IPP_IND_IO_FA_BIT3_SELECT_INPUT DAISY Register

pub const fn flexspi2_ipp_ind_io_fb_bit0_select_input( self, ) -> Reg<Flexspi2IppIndIoFbBit0SelectInput, RW>

FLEXSPI2_IPP_IND_IO_FB_BIT0_SELECT_INPUT DAISY Register

pub const fn flexspi2_ipp_ind_io_fb_bit1_select_input( self, ) -> Reg<Flexspi2IppIndIoFbBit1SelectInput, RW>

FLEXSPI2_IPP_IND_IO_FB_BIT1_SELECT_INPUT DAISY Register

pub const fn flexspi2_ipp_ind_io_fb_bit2_select_input( self, ) -> Reg<Flexspi2IppIndIoFbBit2SelectInput, RW>

FLEXSPI2_IPP_IND_IO_FB_BIT2_SELECT_INPUT DAISY Register

pub const fn flexspi2_ipp_ind_io_fb_bit3_select_input( self, ) -> Reg<Flexspi2IppIndIoFbBit3SelectInput, RW>

FLEXSPI2_IPP_IND_IO_FB_BIT3_SELECT_INPUT DAISY Register

pub const fn flexspi2_ipp_ind_sck_fa_select_input( self, ) -> Reg<Flexspi2IppIndSckFaSelectInput, RW>

FLEXSPI2_IPP_IND_SCK_FA_SELECT_INPUT DAISY Register

pub const fn flexspi2_ipp_ind_sck_fb_select_input( self, ) -> Reg<Flexspi2IppIndSckFbSelectInput, RW>

FLEXSPI2_IPP_IND_SCK_FB_SELECT_INPUT DAISY Register

pub const fn gpt1_ipp_ind_capin1_select_input( self, ) -> Reg<Gpt1IppIndCapin1SelectInput, RW>

GPT1_IPP_IND_CAPIN1_SELECT_INPUT DAISY Register

pub const fn gpt1_ipp_ind_capin2_select_input( self, ) -> Reg<Gpt1IppIndCapin2SelectInput, RW>

GPT1_IPP_IND_CAPIN2_SELECT_INPUT DAISY Register

pub const fn gpt1_ipp_ind_clkin_select_input( self, ) -> Reg<Gpt1IppIndClkinSelectInput, RW>

GPT1_IPP_IND_CLKIN_SELECT_INPUT DAISY Register

pub const fn gpt2_ipp_ind_capin1_select_input( self, ) -> Reg<Gpt2IppIndCapin1SelectInput, RW>

GPT2_IPP_IND_CAPIN1_SELECT_INPUT DAISY Register

pub const fn gpt2_ipp_ind_capin2_select_input( self, ) -> Reg<Gpt2IppIndCapin2SelectInput, RW>

GPT2_IPP_IND_CAPIN2_SELECT_INPUT DAISY Register

pub const fn gpt2_ipp_ind_clkin_select_input( self, ) -> Reg<Gpt2IppIndClkinSelectInput, RW>

GPT2_IPP_IND_CLKIN_SELECT_INPUT DAISY Register

pub const fn sai3_ipg_clk_sai_mclk_select_input_2( self, ) -> Reg<Sai3IpgClkSaiMclkSelectInput2, RW>

SAI3_IPG_CLK_SAI_MCLK_SELECT_INPUT_2 DAISY Register

pub const fn sai3_ipp_ind_sai_rxbclk_select_input( self, ) -> Reg<Sai3IppIndSaiRxbclkSelectInput, RW>

SAI3_IPP_IND_SAI_RXBCLK_SELECT_INPUT DAISY Register

pub const fn sai3_ipp_ind_sai_rxdata_select_input_0( self, ) -> Reg<Sai3IppIndSaiRxdataSelectInput0, RW>

SAI3_IPP_IND_SAI_RXDATA_SELECT_INPUT_0 DAISY Register

pub const fn sai3_ipp_ind_sai_rxsync_select_input( self, ) -> Reg<Sai3IppIndSaiRxsyncSelectInput, RW>

SAI3_IPP_IND_SAI_RXSYNC_SELECT_INPUT DAISY Register

pub const fn sai3_ipp_ind_sai_txbclk_select_input( self, ) -> Reg<Sai3IppIndSaiTxbclkSelectInput, RW>

SAI3_IPP_IND_SAI_TXBCLK_SELECT_INPUT DAISY Register

pub const fn sai3_ipp_ind_sai_txsync_select_input( self, ) -> Reg<Sai3IppIndSaiTxsyncSelectInput, RW>

SAI3_IPP_IND_SAI_TXSYNC_SELECT_INPUT DAISY Register

pub const fn semc_i_ipp_ind_dqs4_select_input( self, ) -> Reg<SemcIIppIndDqs4SelectInput, RW>

SEMC_I_IPP_IND_DQS4_SELECT_INPUT DAISY Register

pub const fn canfd_ipp_ind_canrx_select_input( self, ) -> Reg<CanfdIppIndCanrxSelectInput, RW>

CANFD_IPP_IND_CANRX_SELECT_INPUT DAISY Register

Trait Implementations

impl Clone for Iomuxc

fn clone(&self) -> Iomuxc

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl PartialEq for Iomuxc

fn eq(&self, other: &Iomuxc) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Iomuxc

impl Eq for Iomuxc

impl Send for Iomuxc

impl StructuralPartialEq for Iomuxc

impl Sync for Iomuxc