Struct Gpr1 

#[repr(transparent)]
pub struct Gpr1(pub u32);

GPR1 General Purpose Register

Tuple Fields

0: u32

Implementations

impl Gpr1

pub const fn sai1_mclk1_sel(&self) -> Sai1Mclk1Sel

SAI1 MCLK1 source select

pub const fn set_sai1_mclk1_sel(&mut self, val: Sai1Mclk1Sel)

SAI1 MCLK1 source select

pub const fn sai1_mclk2_sel(&self) -> Sai1Mclk2Sel

SAI1 MCLK2 source select

pub const fn set_sai1_mclk2_sel(&mut self, val: Sai1Mclk2Sel)

SAI1 MCLK2 source select

pub const fn sai1_mclk3_sel(&self) -> Sai1Mclk3Sel

SAI1 MCLK3 source select

pub const fn set_sai1_mclk3_sel(&mut self, val: Sai1Mclk3Sel)

SAI1 MCLK3 source select

pub const fn sai2_mclk3_sel(&self) -> Sai2Mclk3Sel

SAI2 MCLK3 source select

pub const fn set_sai2_mclk3_sel(&mut self, val: Sai2Mclk3Sel)

SAI2 MCLK3 source select

pub const fn sai3_mclk3_sel(&self) -> Sai3Mclk3Sel

SAI3 MCLK3 source select

pub const fn set_sai3_mclk3_sel(&mut self, val: Sai3Mclk3Sel)

SAI3 MCLK3 source select

pub const fn gint(&self) -> Gint

Global Interrupt

pub const fn set_gint(&mut self, val: Gint)

Global Interrupt

pub const fn enet1_clk_sel(&self) -> Enet1ClkSel

ENET1 reference clock mode select.

pub const fn set_enet1_clk_sel(&mut self, val: Enet1ClkSel)

ENET1 reference clock mode select.

pub const fn enet2_clk_sel(&self) -> Enet2ClkSel

ENET2 reference clock mode select.

pub const fn set_enet2_clk_sel(&mut self, val: Enet2ClkSel)

ENET2 reference clock mode select.

pub const fn enet1_tx_clk_dir(&self) -> Enet1TxClkDir

ENET1_TX_CLK data direction control

pub const fn set_enet1_tx_clk_dir(&mut self, val: Enet1TxClkDir)

ENET1_TX_CLK data direction control

pub const fn enet2_tx_clk_dir(&self) -> Enet2TxClkDir

ENET2_TX_CLK data direction control

pub const fn set_enet2_tx_clk_dir(&mut self, val: Enet2TxClkDir)

ENET2_TX_CLK data direction control

pub const fn sai1_mclk_dir(&self) -> Sai1MclkDir

sai1.MCLK signal direction control

pub const fn set_sai1_mclk_dir(&mut self, val: Sai1MclkDir)

sai1.MCLK signal direction control

pub const fn sai2_mclk_dir(&self) -> Sai2MclkDir

sai2.MCLK signal direction control

pub const fn set_sai2_mclk_dir(&mut self, val: Sai2MclkDir)

sai2.MCLK signal direction control

pub const fn sai3_mclk_dir(&self) -> Sai3MclkDir

sai3.MCLK signal direction control

pub const fn set_sai3_mclk_dir(&mut self, val: Sai3MclkDir)

sai3.MCLK signal direction control

pub const fn exc_mon(&self) -> ExcMon

Exclusive monitor response select of illegal command

pub const fn set_exc_mon(&mut self, val: ExcMon)

Exclusive monitor response select of illegal command

pub const fn enet_ipg_clk_s_en(&self) -> EnetIpgClkSEn

ENET and ENET2 ipg_clk_s clock gating enable

pub const fn set_enet_ipg_clk_s_en(&mut self, val: EnetIpgClkSEn)

ENET and ENET2 ipg_clk_s clock gating enable

pub const fn cm7_force_hclk_en(&self) -> Cm7ForceHclkEn

Arm CM7 platform AHB clock enable

pub const fn set_cm7_force_hclk_en(&mut self, val: Cm7ForceHclkEn)

Arm CM7 platform AHB clock enable

Trait Implementations

impl Clone for Gpr1

fn clone(&self) -> Gpr1

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for Gpr1

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Default for Gpr1

fn default() -> Gpr1

Returns the “default value” for a type.

impl PartialEq for Gpr1

fn eq(&self, other: &Gpr1) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Gpr1

impl Eq for Gpr1

impl StructuralPartialEq for Gpr1