#[repr(transparent)]pub struct Vdctrl0(pub u32);Expand description
LCDIF VSYNC Mode and Dotclk Mode Control Register0
Tuple Fields§
§0: u32Implementations§
Source§impl Vdctrl0
impl Vdctrl0
Sourcepub const fn vsync_pulse_width(&self) -> u32
pub const fn vsync_pulse_width(&self) -> u32
Number of units for which VSYNC signal is active
Sourcepub const fn set_vsync_pulse_width(&mut self, val: u32)
pub const fn set_vsync_pulse_width(&mut self, val: u32)
Number of units for which VSYNC signal is active
Sourcepub const fn half_line_mode(&self) -> bool
pub const fn half_line_mode(&self) -> bool
When this bit is 0, the first field (VSYNC period) will end in half a horizontal line and the second field will begin with half a horizontal line
Sourcepub const fn set_half_line_mode(&mut self, val: bool)
pub const fn set_half_line_mode(&mut self, val: bool)
When this bit is 0, the first field (VSYNC period) will end in half a horizontal line and the second field will begin with half a horizontal line
Sourcepub const fn half_line(&self) -> bool
pub const fn half_line(&self) -> bool
Setting this bit to 1 will make the total VSYNC period equal to the VSYNC_PERIOD field plus half the HORIZONTAL_PERIOD field (i
Sourcepub const fn set_half_line(&mut self, val: bool)
pub const fn set_half_line(&mut self, val: bool)
Setting this bit to 1 will make the total VSYNC period equal to the VSYNC_PERIOD field plus half the HORIZONTAL_PERIOD field (i
Sourcepub const fn vsync_pulse_width_unit(&self) -> bool
pub const fn vsync_pulse_width_unit(&self) -> bool
Default 0 for counting VSYNC_PULSE_WIDTH in terms of DISPLAY CLOCK (pix_clk) cycles
Sourcepub const fn set_vsync_pulse_width_unit(&mut self, val: bool)
pub const fn set_vsync_pulse_width_unit(&mut self, val: bool)
Default 0 for counting VSYNC_PULSE_WIDTH in terms of DISPLAY CLOCK (pix_clk) cycles
Sourcepub const fn vsync_period_unit(&self) -> bool
pub const fn vsync_period_unit(&self) -> bool
Default 0 for counting VSYNC_PERIOD in terms of DISPLAY CLOCK (pix_clk) cycles
Sourcepub const fn set_vsync_period_unit(&mut self, val: bool)
pub const fn set_vsync_period_unit(&mut self, val: bool)
Default 0 for counting VSYNC_PERIOD in terms of DISPLAY CLOCK (pix_clk) cycles
Sourcepub const fn enable_pol(&self) -> bool
pub const fn enable_pol(&self) -> bool
Default 0 active low during valid data transfer on each horizontal line.
Sourcepub const fn set_enable_pol(&mut self, val: bool)
pub const fn set_enable_pol(&mut self, val: bool)
Default 0 active low during valid data transfer on each horizontal line.
Sourcepub const fn dotclk_pol(&self) -> bool
pub const fn dotclk_pol(&self) -> bool
Default is data launched at negative edge of DOTCLK and captured at positive edge
Sourcepub const fn set_dotclk_pol(&mut self, val: bool)
pub const fn set_dotclk_pol(&mut self, val: bool)
Default is data launched at negative edge of DOTCLK and captured at positive edge
Sourcepub const fn hsync_pol(&self) -> bool
pub const fn hsync_pol(&self) -> bool
Default 0 active low during HSYNC_PULSE_WIDTH time and will be high during the rest of the HSYNC period
Sourcepub const fn set_hsync_pol(&mut self, val: bool)
pub const fn set_hsync_pol(&mut self, val: bool)
Default 0 active low during HSYNC_PULSE_WIDTH time and will be high during the rest of the HSYNC period
Sourcepub const fn vsync_pol(&self) -> bool
pub const fn vsync_pol(&self) -> bool
Default 0 active low during VSYNC_PULSE_WIDTH time and will be high during the rest of the VSYNC period
Sourcepub const fn set_vsync_pol(&mut self, val: bool)
pub const fn set_vsync_pol(&mut self, val: bool)
Default 0 active low during VSYNC_PULSE_WIDTH time and will be high during the rest of the VSYNC period
Sourcepub const fn enable_present(&self) -> bool
pub const fn enable_present(&self) -> bool
Setting this bit to 1 will make the hardware generate the ENABLE signal in the DOTCLK mode, thereby making it the true RGB interface along with the remaining three signals VSYNC, HSYNC and DOTCLK
Sourcepub const fn set_enable_present(&mut self, val: bool)
pub const fn set_enable_present(&mut self, val: bool)
Setting this bit to 1 will make the hardware generate the ENABLE signal in the DOTCLK mode, thereby making it the true RGB interface along with the remaining three signals VSYNC, HSYNC and DOTCLK