#[repr(transparent)]pub struct Vdctrl3(pub u32);Expand description
LCDIF VSYNC Mode and Dotclk Mode Control Register3
Tuple Fields§
§0: u32Implementations§
Source§impl Vdctrl3
impl Vdctrl3
Sourcepub const fn vertical_wait_cnt(&self) -> u16
pub const fn vertical_wait_cnt(&self) -> u16
In the VSYNC interface mode, wait for this number of DISPLAY CLOCK (pix_clk) cycles from the falling VSYNC edge (or rising if VSYNC_POL is 1) before starting LCD transactions and is applicable only if WAIT_FOR_VSYNC_EDGE is set
Sourcepub const fn set_vertical_wait_cnt(&mut self, val: u16)
pub const fn set_vertical_wait_cnt(&mut self, val: u16)
In the VSYNC interface mode, wait for this number of DISPLAY CLOCK (pix_clk) cycles from the falling VSYNC edge (or rising if VSYNC_POL is 1) before starting LCD transactions and is applicable only if WAIT_FOR_VSYNC_EDGE is set
Sourcepub const fn horizontal_wait_cnt(&self) -> u16
pub const fn horizontal_wait_cnt(&self) -> u16
In the DOTCLK mode, wait for this number of clocks from falling edge (or rising if HSYNC_POL is 1) of HSYNC signal to account for horizontal back porch plus the number of DOTCLKs before the moving picture information begins
Sourcepub const fn set_horizontal_wait_cnt(&mut self, val: u16)
pub const fn set_horizontal_wait_cnt(&mut self, val: u16)
In the DOTCLK mode, wait for this number of clocks from falling edge (or rising if HSYNC_POL is 1) of HSYNC signal to account for horizontal back porch plus the number of DOTCLKs before the moving picture information begins
Sourcepub const fn vsync_only(&self) -> bool
pub const fn vsync_only(&self) -> bool
This bit must be set to 1 in the VSYNC mode of operation, and 0 in the DOTCLK mode of operation.
Sourcepub const fn set_vsync_only(&mut self, val: bool)
pub const fn set_vsync_only(&mut self, val: bool)
This bit must be set to 1 in the VSYNC mode of operation, and 0 in the DOTCLK mode of operation.
Sourcepub const fn mux_sync_signals(&self) -> bool
pub const fn mux_sync_signals(&self) -> bool
When this bit is set, the LCDIF block will internally mux HSYNC with LCD_D14, DOTCLK with LCD_D13 and ENABLE with LCD_D12, otherwise these signals will go out on separate pins
Sourcepub const fn set_mux_sync_signals(&mut self, val: bool)
pub const fn set_mux_sync_signals(&mut self, val: bool)
When this bit is set, the LCDIF block will internally mux HSYNC with LCD_D14, DOTCLK with LCD_D13 and ENABLE with LCD_D12, otherwise these signals will go out on separate pins