#[repr(transparent)]pub struct Vdctrl4(pub u32);Expand description
LCDIF VSYNC Mode and Dotclk Mode Control Register4
Tuple Fields§
§0: u32Implementations§
Source§impl Vdctrl4
impl Vdctrl4
Sourcepub const fn dotclk_h_valid_data_cnt(&self) -> u32
pub const fn dotclk_h_valid_data_cnt(&self) -> u32
Total number of DISPLAY CLOCK (pix_clk) cycles on each horizontal line that carry valid data in DOTCLK mode
Sourcepub const fn set_dotclk_h_valid_data_cnt(&mut self, val: u32)
pub const fn set_dotclk_h_valid_data_cnt(&mut self, val: u32)
Total number of DISPLAY CLOCK (pix_clk) cycles on each horizontal line that carry valid data in DOTCLK mode
Sourcepub const fn sync_signals_on(&self) -> bool
pub const fn sync_signals_on(&self) -> bool
Set this field to 1 if the LCD controller requires that the VSYNC or VSYNC/HSYNC/DOTCLK control signals should be active at least one frame before the data transfers actually start and remain active at least one frame after the data transfers end
Sourcepub const fn set_sync_signals_on(&mut self, val: bool)
pub const fn set_sync_signals_on(&mut self, val: bool)
Set this field to 1 if the LCD controller requires that the VSYNC or VSYNC/HSYNC/DOTCLK control signals should be active at least one frame before the data transfers actually start and remain active at least one frame after the data transfers end
Sourcepub const fn dotclk_dly_sel(&self) -> u8
pub const fn dotclk_dly_sel(&self) -> u8
This bitfield selects the amount of time by which the DOTCLK signal should be delayed before coming out of the LCD_DOTCK pin
Sourcepub const fn set_dotclk_dly_sel(&mut self, val: u8)
pub const fn set_dotclk_dly_sel(&mut self, val: u8)
This bitfield selects the amount of time by which the DOTCLK signal should be delayed before coming out of the LCD_DOTCK pin