Struct Esr1 

#[repr(transparent)]
pub struct Esr1(pub u32);

Error and Status 1 Register

Tuple Fields

0: u32

Implementations

impl Esr1

pub const fn wakint(&self) -> Wakint

When FLEXCAN is Stop Mode and a recessive to dominant transition is detected on the CAN bus and if the WAK_MSK bit in the MCR Register is set, an interrupt is generated to the Arm

pub const fn set_wakint(&mut self, val: Wakint)

When FLEXCAN is Stop Mode and a recessive to dominant transition is detected on the CAN bus and if the WAK_MSK bit in the MCR Register is set, an interrupt is generated to the Arm

pub const fn errint(&self) -> Errint

This bit indicates that at least one of the Error Bits (bits 15-10) is set

pub const fn set_errint(&mut self, val: Errint)

This bit indicates that at least one of the Error Bits (bits 15-10) is set

pub const fn boffint(&self) -> Boffint

This bit is set when FLEXCAN enters ‘Bus Off’ state

pub const fn set_boffint(&mut self, val: Boffint)

This bit is set when FLEXCAN enters ‘Bus Off’ state

pub const fn rx(&self) -> Rx

This bit indicates if FlexCAN is receiving a message. Refer to .

pub const fn set_rx(&mut self, val: Rx)

This bit indicates if FlexCAN is receiving a message. Refer to .

pub const fn fltconf(&self) -> Fltconf

If the LOM bit in the Control Register is asserted, after some delay that depends on the CAN bit timing the FLT_CONF field will indicate “Error Passive”

pub const fn set_fltconf(&mut self, val: Fltconf)

If the LOM bit in the Control Register is asserted, after some delay that depends on the CAN bit timing the FLT_CONF field will indicate “Error Passive”

pub const fn tx(&self) -> Tx

This bit indicates if FLEXCAN is transmitting a message.Refer to .

pub const fn set_tx(&mut self, val: Tx)

This bit indicates if FLEXCAN is transmitting a message.Refer to .

pub const fn idle(&self) -> Idle

This bit indicates when CAN bus is in IDLE state.Refer to .

pub const fn set_idle(&mut self, val: Idle)

This bit indicates when CAN bus is in IDLE state.Refer to .

pub const fn rxwrn(&self) -> Rxwrn

This bit indicates when repetitive errors are occurring during message reception.

pub const fn set_rxwrn(&mut self, val: Rxwrn)

This bit indicates when repetitive errors are occurring during message reception.

pub const fn txwrn(&self) -> Txwrn

This bit indicates when repetitive errors are occurring during message transmission.

pub const fn set_txwrn(&mut self, val: Txwrn)

This bit indicates when repetitive errors are occurring during message transmission.

pub const fn stferr(&self) -> Stferr

This bit indicates that a Stuffing Error has been detected.

pub const fn set_stferr(&mut self, val: Stferr)

This bit indicates that a Stuffing Error has been detected.

pub const fn frmerr(&self) -> Frmerr

This bit indicates that a Form Error has been detected by the receiver node, i

pub const fn set_frmerr(&mut self, val: Frmerr)

This bit indicates that a Form Error has been detected by the receiver node, i

pub const fn crcerr(&self) -> Crcerr

This bit indicates that a CRC Error has been detected by the receiver node, i

pub const fn set_crcerr(&mut self, val: Crcerr)

This bit indicates that a CRC Error has been detected by the receiver node, i

pub const fn ackerr(&self) -> Ackerr

This bit indicates that an Acknowledge Error has been detected by the transmitter node, i

pub const fn set_ackerr(&mut self, val: Ackerr)

This bit indicates that an Acknowledge Error has been detected by the transmitter node, i

pub const fn bit0err(&self) -> Bit0err

This bit indicates when an inconsistency occurs between the transmitted and the received bit in a message

pub const fn set_bit0err(&mut self, val: Bit0err)

This bit indicates when an inconsistency occurs between the transmitted and the received bit in a message

pub const fn bit1err(&self) -> Bit1err

This bit indicates when an inconsistency occurs between the transmitted and the received bit in a message

pub const fn set_bit1err(&mut self, val: Bit1err)

This bit indicates when an inconsistency occurs between the transmitted and the received bit in a message

pub const fn rwrnint(&self) -> Rwrnint

If the WRN_EN bit in MCR is asserted, the RWRN_INT bit is set when the RX_WRN flag transition from ‘0’ to ‘1’, meaning that the Rx error counters reached 96

pub const fn set_rwrnint(&mut self, val: Rwrnint)

If the WRN_EN bit in MCR is asserted, the RWRN_INT bit is set when the RX_WRN flag transition from ‘0’ to ‘1’, meaning that the Rx error counters reached 96

pub const fn twrnint(&self) -> Twrnint

If the WRN_EN bit in MCR is asserted, the TWRN_INT bit is set when the TX_WRN flag transition from ‘0’ to ‘1’, meaning that the Tx error counter reached 96

pub const fn set_twrnint(&mut self, val: Twrnint)

If the WRN_EN bit in MCR is asserted, the TWRN_INT bit is set when the TX_WRN flag transition from ‘0’ to ‘1’, meaning that the Tx error counter reached 96

pub const fn synch(&self) -> Synch

This read-only flag indicates whether the FlexCAN is synchronized to the CAN bus and able to participate in the communication process

pub const fn set_synch(&mut self, val: Synch)

This read-only flag indicates whether the FlexCAN is synchronized to the CAN bus and able to participate in the communication process

Trait Implementations

impl Clone for Esr1

fn clone(&self) -> Esr1

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for Esr1

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Default for Esr1

fn default() -> Esr1

Returns the “default value” for a type.

impl PartialEq for Esr1

fn eq(&self, other: &Esr1) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Esr1

impl Eq for Esr1

impl StructuralPartialEq for Esr1