Struct Mcr 

#[repr(transparent)]
pub struct Mcr(pub u32);

Module Configuration Register

Tuple Fields

0: u32

Implementations

impl Mcr

pub const fn maxmb(&self) -> u8

This 7-bit field defines the number of the last Message Buffers that will take part in the matching and arbitration processes

pub const fn set_maxmb(&mut self, val: u8)

This 7-bit field defines the number of the last Message Buffers that will take part in the matching and arbitration processes

pub const fn idam(&self) -> Idam

This 2-bit field identifies the format of the elements of the Rx FIFO filter table, as shown below

pub const fn set_idam(&mut self, val: Idam)

This 2-bit field identifies the format of the elements of the Rx FIFO filter table, as shown below

pub const fn aen(&self) -> Aen

This bit is supplied for backwards compatibility reasons

pub const fn set_aen(&mut self, val: Aen)

This bit is supplied for backwards compatibility reasons

pub const fn lprioen(&self) -> Lprioen

This bit is provided for backwards compatibility reasons

pub const fn set_lprioen(&mut self, val: Lprioen)

This bit is provided for backwards compatibility reasons

pub const fn irmq(&self) -> Irmq

This bit indicates whether Rx matching process will be based either on individual masking and queue or on masking scheme with RXMGMASK, RX14MASK and RX15MASK, RXFGMASK

pub const fn set_irmq(&mut self, val: Irmq)

This bit indicates whether Rx matching process will be based either on individual masking and queue or on masking scheme with RXMGMASK, RX14MASK and RX15MASK, RXFGMASK

pub const fn srxdis(&self) -> Srxdis

This bit defines whether FlexCAN is allowed to receive frames transmitted by itself

pub const fn set_srxdis(&mut self, val: Srxdis)

This bit defines whether FlexCAN is allowed to receive frames transmitted by itself

pub const fn waksrc(&self) -> Waksrc

This bit defines whether the integrated low-pass filter is applied to protect the FLEXCAN_RX input from spurious wake up

pub const fn set_waksrc(&mut self, val: Waksrc)

This bit defines whether the integrated low-pass filter is applied to protect the FLEXCAN_RX input from spurious wake up

pub const fn lpmack(&self) -> Lpmack

This read-only bit indicates that FLEXCAN is either in Disable Mode or Stop Mode

pub const fn set_lpmack(&mut self, val: Lpmack)

This read-only bit indicates that FLEXCAN is either in Disable Mode or Stop Mode

pub const fn wrnen(&self) -> Wrnen

When asserted, this bit enables the generation of the TWRN_INT and RWRN_INT flags in the Error and Status Register

pub const fn set_wrnen(&mut self, val: Wrnen)

When asserted, this bit enables the generation of the TWRN_INT and RWRN_INT flags in the Error and Status Register

pub const fn slfwak(&self) -> Slfwak

This bit enables the Self Wake Up feature when FLEXCAN is in Stop Mode

pub const fn set_slfwak(&mut self, val: Slfwak)

This bit enables the Self Wake Up feature when FLEXCAN is in Stop Mode

pub const fn supv(&self) -> Supv

This bit configures some of the FLEXCAN registers to be either in Supervisor or User Mode

pub const fn set_supv(&mut self, val: Supv)

This bit configures some of the FLEXCAN registers to be either in Supervisor or User Mode

pub const fn frzack(&self) -> Frzack

This read-only bit indicates that FLEXCAN is in Freeze Mode and its prescaler is stopped

pub const fn set_frzack(&mut self, val: Frzack)

This read-only bit indicates that FLEXCAN is in Freeze Mode and its prescaler is stopped

pub const fn softrst(&self) -> Softrst

When this bit is asserted, FlexCAN resets its internal state machines and some of the memory mapped registers

pub const fn set_softrst(&mut self, val: Softrst)

When this bit is asserted, FlexCAN resets its internal state machines and some of the memory mapped registers

pub const fn wakmsk(&self) -> Wakmsk

This bit enables the Wake Up Interrupt generation.

pub const fn set_wakmsk(&mut self, val: Wakmsk)

This bit enables the Wake Up Interrupt generation.

pub const fn notrdy(&self) -> Notrdy

This read-only bit indicates that FLEXCAN is either in Disable Mode, Stop Mode or Freeze Mode

pub const fn set_notrdy(&mut self, val: Notrdy)

This read-only bit indicates that FLEXCAN is either in Disable Mode, Stop Mode or Freeze Mode

pub const fn halt(&self) -> Halt

Assertion of this bit puts the FLEXCAN module into Freeze Mode

pub const fn set_halt(&mut self, val: Halt)

Assertion of this bit puts the FLEXCAN module into Freeze Mode

pub const fn rfen(&self) -> Rfen

This bit controls whether the Rx FIFO feature is enabled or not

pub const fn set_rfen(&mut self, val: Rfen)

This bit controls whether the Rx FIFO feature is enabled or not

pub const fn frz(&self) -> Frz

The FRZ bit specifies the FLEXCAN behavior when the HALT bit in the MCR Register is set or when Debug Mode is requested at Arm level

pub const fn set_frz(&mut self, val: Frz)

The FRZ bit specifies the FLEXCAN behavior when the HALT bit in the MCR Register is set or when Debug Mode is requested at Arm level

pub const fn mdis(&self) -> Mdis

This bit controls whether FLEXCAN is enabled or not

pub const fn set_mdis(&mut self, val: Mdis)

This bit controls whether FLEXCAN is enabled or not

Trait Implementations

impl Clone for Mcr

fn clone(&self) -> Mcr

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for Mcr

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Default for Mcr

fn default() -> Mcr

Returns the “default value” for a type.

impl PartialEq for Mcr

fn eq(&self, other: &Mcr) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Mcr

impl Eq for Mcr

impl StructuralPartialEq for Mcr