#[repr(transparent)]pub struct Cmeor(pub u32);Expand description
CCM Module Enable Overide Register
Tuple Fields§
§0: u32Implementations§
Source§impl Cmeor
impl Cmeor
Sourcepub const fn mod_en_ov_gpt(&self) -> ModEnOvGpt
pub const fn mod_en_ov_gpt(&self) -> ModEnOvGpt
Overide clock enable signal from GPT - clock will not be gated based on GPT’s signal ‘ipg_enable_clk’
Sourcepub const fn set_mod_en_ov_gpt(&mut self, val: ModEnOvGpt)
pub const fn set_mod_en_ov_gpt(&mut self, val: ModEnOvGpt)
Overide clock enable signal from GPT - clock will not be gated based on GPT’s signal ‘ipg_enable_clk’
Sourcepub const fn mod_en_ov_pit(&self) -> ModEnOvPit
pub const fn mod_en_ov_pit(&self) -> ModEnOvPit
Overide clock enable signal from PIT - clock will not be gated based on PIT’s signal ‘ipg_enable_clk’
Sourcepub const fn set_mod_en_ov_pit(&mut self, val: ModEnOvPit)
pub const fn set_mod_en_ov_pit(&mut self, val: ModEnOvPit)
Overide clock enable signal from PIT - clock will not be gated based on PIT’s signal ‘ipg_enable_clk’
Sourcepub const fn mod_en_usdhc(&self) -> ModEnUsdhc
pub const fn mod_en_usdhc(&self) -> ModEnUsdhc
overide clock enable signal from USDHC.
Sourcepub const fn set_mod_en_usdhc(&mut self, val: ModEnUsdhc)
pub const fn set_mod_en_usdhc(&mut self, val: ModEnUsdhc)
overide clock enable signal from USDHC.
Sourcepub const fn mod_en_ov_trng(&self) -> ModEnOvTrng
pub const fn mod_en_ov_trng(&self) -> ModEnOvTrng
Overide clock enable signal from TRNG
Sourcepub const fn set_mod_en_ov_trng(&mut self, val: ModEnOvTrng)
pub const fn set_mod_en_ov_trng(&mut self, val: ModEnOvTrng)
Overide clock enable signal from TRNG
Sourcepub const fn mod_en_ov_canfd_cpi(&self) -> ModEnOvCanfdCpi
pub const fn mod_en_ov_canfd_cpi(&self) -> ModEnOvCanfdCpi
Overide clock enable signal from FlexCAN3(CANFD) - clock will not be gated based on CAN’s signal ‘enable_clk_cpi’
Sourcepub const fn set_mod_en_ov_canfd_cpi(&mut self, val: ModEnOvCanfdCpi)
pub const fn set_mod_en_ov_canfd_cpi(&mut self, val: ModEnOvCanfdCpi)
Overide clock enable signal from FlexCAN3(CANFD) - clock will not be gated based on CAN’s signal ‘enable_clk_cpi’
Sourcepub const fn mod_en_ov_can2_cpi(&self) -> ModEnOvCan2Cpi
pub const fn mod_en_ov_can2_cpi(&self) -> ModEnOvCan2Cpi
Overide clock enable signal from CAN2 - clock will not be gated based on CAN’s signal ‘enable_clk_cpi’
Sourcepub const fn set_mod_en_ov_can2_cpi(&mut self, val: ModEnOvCan2Cpi)
pub const fn set_mod_en_ov_can2_cpi(&mut self, val: ModEnOvCan2Cpi)
Overide clock enable signal from CAN2 - clock will not be gated based on CAN’s signal ‘enable_clk_cpi’
Sourcepub const fn mod_en_ov_can1_cpi(&self) -> ModEnOvCan1Cpi
pub const fn mod_en_ov_can1_cpi(&self) -> ModEnOvCan1Cpi
Overide clock enable signal from CAN1 - clock will not be gated based on CAN’s signal ‘enable_clk_cpi’
Sourcepub const fn set_mod_en_ov_can1_cpi(&mut self, val: ModEnOvCan1Cpi)
pub const fn set_mod_en_ov_can1_cpi(&mut self, val: ModEnOvCan1Cpi)
Overide clock enable signal from CAN1 - clock will not be gated based on CAN’s signal ‘enable_clk_cpi’