Struct CcmAnalog 

pub struct CcmAnalog { /* private fields */ }

CCM_ANALOG

Implementations

impl CcmAnalog

pub const unsafe fn from_ptr(ptr: *mut ()) -> Self

pub const fn as_ptr(&self) -> *mut ()

pub const fn pll_arm(self) -> Reg<PllArm, RW>

Analog ARM PLL control Register

pub const fn pll_arm_set(self) -> Reg<PllArmSet, RW>

Analog ARM PLL control Register

pub const fn pll_arm_clr(self) -> Reg<PllArmClr, RW>

Analog ARM PLL control Register

pub const fn pll_arm_tog(self) -> Reg<PllArmTog, RW>

Analog ARM PLL control Register

pub const fn pll_usb1(self) -> Reg<PllUsb1, RW>

Analog USB1 480MHz PLL Control Register

pub const fn pll_usb1_set(self) -> Reg<PllUsb1Set, RW>

Analog USB1 480MHz PLL Control Register

pub const fn pll_usb1_clr(self) -> Reg<PllUsb1Clr, RW>

Analog USB1 480MHz PLL Control Register

pub const fn pll_usb1_tog(self) -> Reg<PllUsb1Tog, RW>

Analog USB1 480MHz PLL Control Register

pub const fn pll_usb2(self) -> Reg<PllUsb2, RW>

Analog USB2 480MHz PLL Control Register

pub const fn pll_usb2_set(self) -> Reg<PllUsb2Set, RW>

Analog USB2 480MHz PLL Control Register

pub const fn pll_usb2_clr(self) -> Reg<PllUsb2Clr, RW>

Analog USB2 480MHz PLL Control Register

pub const fn pll_usb2_tog(self) -> Reg<PllUsb2Tog, RW>

Analog USB2 480MHz PLL Control Register

pub const fn pll_sys(self) -> Reg<PllSys, RW>

Analog System PLL Control Register

pub const fn pll_sys_set(self) -> Reg<PllSysSet, RW>

Analog System PLL Control Register

pub const fn pll_sys_clr(self) -> Reg<PllSysClr, RW>

Analog System PLL Control Register

pub const fn pll_sys_tog(self) -> Reg<PllSysTog, RW>

Analog System PLL Control Register

pub const fn pll_sys_ss(self) -> Reg<PllSysSs, RW>

528MHz System PLL Spread Spectrum Register

pub const fn pll_sys_num(self) -> Reg<PllSysNum, RW>

Numerator of 528MHz System PLL Fractional Loop Divider Register

pub const fn pll_sys_denom(self) -> Reg<PllSysDenom, RW>

Denominator of 528MHz System PLL Fractional Loop Divider Register

pub const fn pll_audio(self) -> Reg<PllAudio, RW>

Analog Audio PLL control Register

pub const fn pll_audio_set(self) -> Reg<PllAudioSet, RW>

Analog Audio PLL control Register

pub const fn pll_audio_clr(self) -> Reg<PllAudioClr, RW>

Analog Audio PLL control Register

pub const fn pll_audio_tog(self) -> Reg<PllAudioTog, RW>

Analog Audio PLL control Register

pub const fn pll_audio_num(self) -> Reg<PllAudioNum, RW>

Numerator of Audio PLL Fractional Loop Divider Register

pub const fn pll_audio_denom(self) -> Reg<PllAudioDenom, RW>

Denominator of Audio PLL Fractional Loop Divider Register

pub const fn pll_video(self) -> Reg<PllVideo, RW>

Analog Video PLL control Register

pub const fn pll_video_set(self) -> Reg<PllVideoSet, RW>

Analog Video PLL control Register

pub const fn pll_video_clr(self) -> Reg<PllVideoClr, RW>

Analog Video PLL control Register

pub const fn pll_video_tog(self) -> Reg<PllVideoTog, RW>

Analog Video PLL control Register

pub const fn pll_video_num(self) -> Reg<PllVideoNum, RW>

Numerator of Video PLL Fractional Loop Divider Register

pub const fn pll_video_denom(self) -> Reg<PllVideoDenom, RW>

Denominator of Video PLL Fractional Loop Divider Register

pub const fn pll_enet(self) -> Reg<PllEnet, RW>

Analog ENET PLL Control Register

pub const fn pll_enet_set(self) -> Reg<PllEnetSet, RW>

Analog ENET PLL Control Register

pub const fn pll_enet_clr(self) -> Reg<PllEnetClr, RW>

Analog ENET PLL Control Register

pub const fn pll_enet_tog(self) -> Reg<PllEnetTog, RW>

Analog ENET PLL Control Register

pub const fn pfd_480(self) -> Reg<Pfd480, RW>

480MHz Clock (PLL3) Phase Fractional Divider Control Register

pub const fn pfd_480_set(self) -> Reg<Pfd480Set, RW>

480MHz Clock (PLL3) Phase Fractional Divider Control Register

pub const fn pfd_480_clr(self) -> Reg<Pfd480Clr, RW>

480MHz Clock (PLL3) Phase Fractional Divider Control Register

pub const fn pfd_480_tog(self) -> Reg<Pfd480Tog, RW>

480MHz Clock (PLL3) Phase Fractional Divider Control Register

pub const fn pfd_528(self) -> Reg<Pfd528, RW>

528MHz Clock (PLL2) Phase Fractional Divider Control Register

pub const fn pfd_528_set(self) -> Reg<Pfd528Set, RW>

528MHz Clock (PLL2) Phase Fractional Divider Control Register

pub const fn pfd_528_clr(self) -> Reg<Pfd528Clr, RW>

528MHz Clock (PLL2) Phase Fractional Divider Control Register

pub const fn pfd_528_tog(self) -> Reg<Pfd528Tog, RW>

528MHz Clock (PLL2) Phase Fractional Divider Control Register

pub const fn misc0(self) -> Reg<Misc0, RW>

Miscellaneous Register 0

pub const fn misc0_set(self) -> Reg<Misc0Set, RW>

Miscellaneous Register 0

pub const fn misc0_clr(self) -> Reg<Misc0Clr, RW>

Miscellaneous Register 0

pub const fn misc0_tog(self) -> Reg<Misc0Tog, RW>

Miscellaneous Register 0

pub const fn misc1(self) -> Reg<Misc1, RW>

Miscellaneous Register 1

pub const fn misc1_set(self) -> Reg<Misc1Set, RW>

Miscellaneous Register 1

pub const fn misc1_clr(self) -> Reg<Misc1Clr, RW>

Miscellaneous Register 1

pub const fn misc1_tog(self) -> Reg<Misc1Tog, RW>

Miscellaneous Register 1

pub const fn misc2(self) -> Reg<Misc2, RW>

Miscellaneous Register 2

pub const fn misc2_set(self) -> Reg<Misc2Set, RW>

Miscellaneous Register 2

pub const fn misc2_clr(self) -> Reg<Misc2Clr, RW>

Miscellaneous Register 2

pub const fn misc2_tog(self) -> Reg<Misc2Tog, RW>

Miscellaneous Register 2

Trait Implementations

impl Clone for CcmAnalog

fn clone(&self) -> CcmAnalog

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl PartialEq for CcmAnalog

fn eq(&self, other: &CcmAnalog) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for CcmAnalog

impl Eq for CcmAnalog

impl Send for CcmAnalog

impl StructuralPartialEq for CcmAnalog

impl Sync for CcmAnalog