Struct Reg0 

#[repr(transparent)]
pub struct Reg0(pub u32);

DCDC Register 0

Tuple Fields

0: u32

Implementations

impl Reg0

pub const fn pwd_zcd(&self) -> PwdZcd

Power Down Zero Cross Detection

pub const fn set_pwd_zcd(&mut self, val: PwdZcd)

Power Down Zero Cross Detection

pub const fn disable_auto_clk_switch(&self) -> DisableAutoClkSwitch

Disable Auto Clock Switch

pub const fn set_disable_auto_clk_switch(&mut self, val: DisableAutoClkSwitch)

Disable Auto Clock Switch

pub const fn sel_clk(&self) -> SelClk

Select Clock

pub const fn set_sel_clk(&mut self, val: SelClk)

Select Clock

pub const fn pwd_osc_int(&self) -> PwdOscInt

Power down internal osc

pub const fn set_pwd_osc_int(&mut self, val: PwdOscInt)

Power down internal osc

pub const fn pwd_cur_sns_cmp(&self) -> PwdCurSnsCmp

Power down signal of the current detector.

pub const fn set_pwd_cur_sns_cmp(&mut self, val: PwdCurSnsCmp)

Power down signal of the current detector.

pub const fn cur_sns_thrsh(&self) -> CurSnsThrsh

Current Sense (detector) Threshold

pub const fn set_cur_sns_thrsh(&mut self, val: CurSnsThrsh)

Current Sense (detector) Threshold

pub const fn pwd_overcur_det(&self) -> PwdOvercurDet

Power down overcurrent detection comparator

pub const fn set_pwd_overcur_det(&mut self, val: PwdOvercurDet)

Power down overcurrent detection comparator

pub const fn overcur_trig_adj(&self) -> OvercurTrigAdj

Overcurrent Trigger Adjust

pub const fn set_overcur_trig_adj(&mut self, val: OvercurTrigAdj)

Overcurrent Trigger Adjust

pub const fn pwd_cmp_batt_det(&self) -> PwdCmpBattDet

Power Down Battery Detection Comparator

pub const fn set_pwd_cmp_batt_det(&mut self, val: PwdCmpBattDet)

Power Down Battery Detection Comparator

pub const fn en_lp_overload_sns(&self) -> bool

Low Power Overload Sense Enable

pub const fn set_en_lp_overload_sns(&mut self, val: bool)

Low Power Overload Sense Enable

pub const fn pwd_high_volt_det(&self) -> PwdHighVoltDet

Power Down High Voltage Detection

pub const fn set_pwd_high_volt_det(&mut self, val: PwdHighVoltDet)

Power Down High Voltage Detection

pub const fn lp_overload_thrsh(&self) -> LpOverloadThrsh

Low Power Overload Threshold

pub const fn set_lp_overload_thrsh(&mut self, val: LpOverloadThrsh)

Low Power Overload Threshold

pub const fn lp_overload_freq_sel(&self) -> LpOverloadFreqSel

Low Power Overload Frequency Select

pub const fn set_lp_overload_freq_sel(&mut self, val: LpOverloadFreqSel)

Low Power Overload Frequency Select

pub const fn lp_high_hys(&self) -> LpHighHys

Low Power High Hysteric Value

pub const fn set_lp_high_hys(&mut self, val: LpHighHys)

Low Power High Hysteric Value

pub const fn pwd_cmp_offset(&self) -> PwdCmpOffset

Power down output range comparator

pub const fn set_pwd_cmp_offset(&mut self, val: PwdCmpOffset)

Power down output range comparator

pub const fn xtalok_disable(&self) -> XtalokDisable

Disable xtalok detection circuit

pub const fn set_xtalok_disable(&mut self, val: XtalokDisable)

Disable xtalok detection circuit

pub const fn current_alert_reset(&self) -> bool

Reset Current Alert Signal

pub const fn set_current_alert_reset(&mut self, val: bool)

Reset Current Alert Signal

pub const fn xtal_24m_ok(&self) -> Xtal24mOk

24M XTAL OK

pub const fn set_xtal_24m_ok(&mut self, val: Xtal24mOk)

24M XTAL OK

pub const fn sts_dc_ok(&self) -> bool

DCDC Output OK

pub const fn set_sts_dc_ok(&mut self, val: bool)

DCDC Output OK

Trait Implementations

impl Clone for Reg0

fn clone(&self) -> Reg0

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for Reg0

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Default for Reg0

fn default() -> Reg0

Returns the “default value” for a type.

impl PartialEq for Reg0

fn eq(&self, other: &Reg0) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Reg0

impl Eq for Reg0

impl StructuralPartialEq for Reg0