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mimxrt1064

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Module regs

Module regs 

Source

Structsยง

Atcor
Timer Correction Register.
Atcr
Adjustable Timer Control Register.
Atinc
Time-Stamping Clock Period Register.
Atoff
Timer Offset Register.
Atper
Timer Period Register.
Atstmp
Timestamp of Last Transmitted Frame.
Atvr
Timer Value Register.
Ecr
Ethernet Control Register.
Eimr
Interrupt Mask Register.
Eir
Interrupt Event Register.
Ftrl
Frame Truncation Length.
Galr
Descriptor Group Lower Address Register.
Gaur
Descriptor Group Upper Address Register.
Ialr
Descriptor Individual Lower Address Register.
Iaur
Descriptor Individual Upper Address Register.
IeeeRAlign
Frames Received with Alignment Error Statistic Register.
IeeeRCrc
Frames Received with CRC Error Statistic Register.
IeeeRDrop
Frames not Counted Correctly Statistic Register.
IeeeRFdxfc
Flow Control Pause Frames Received Statistic Register.
IeeeRFrameOk
Frames Received OK Statistic Register.
IeeeRMacerr
Receive FIFO Overflow Count Statistic Register.
IeeeROctetsOk
Octet Count for Frames Received without Error Statistic Register.
IeeeT1col
Frames Transmitted with Single Collision Statistic Register.
IeeeTCserr
Frames Transmitted with Carrier Sense Error Statistic Register.
IeeeTDef
Frames Transmitted after Deferral Delay Statistic Register.
IeeeTExcol
Frames Transmitted with Excessive Collisions Statistic Register.
IeeeTFdxfc
Flow Control Pause Frames Transmitted Statistic Register.
IeeeTFrameOk
Frames Transmitted OK Statistic Register.
IeeeTLcol
Frames Transmitted with Late Collision Statistic Register.
IeeeTMacerr
Frames Transmitted with Tx FIFO Underrun Statistic Register.
IeeeTMcol
Frames Transmitted with Multiple Collisions Statistic Register.
IeeeTOctetsOk
Octet Count for Frames Transmitted w/o Error Statistic Register.
IeeeTSqe
Reserved Statistic Register.
Mibc
MIB Control Register.
Mmfr
MII Management Frame Register.
Mrbr
Maximum Receive Buffer Size Register - Ring 0.
Mscr
MII Speed Control Register.
Opd
Opcode/Pause Duration Register.
Palr
Physical Address Lower Register.
Paur
Physical Address Upper Register.
Racc
Receive Accelerator Function Configuration.
Raem
Receive FIFO Almost Empty Threshold.
Rafl
Receive FIFO Almost Full Threshold.
Rcr
Receive Control Register.
Rdar
Receive Descriptor Active Register - Ring 0.
Rdsr
Receive Descriptor Ring 0 Start Register.
RmonRBcPkt
Rx Broadcast Packets Statistic Register.
RmonRCrcAlign
Rx Packets with CRC/Align Error Statistic Register.
RmonRFrag
Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register.
RmonRJab
Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register.
RmonRMcPkt
Rx Multicast Packets Statistic Register.
RmonROctets
Rx Octets Statistic Register.
RmonROversize
Rx Packets Greater Than MAX_FL and Good CRC Statistic Register.
RmonRP64
Rx 64-Byte Packets Statistic Register.
RmonRP65to127
Rx 65- to 127-Byte Packets Statistic Register.
RmonRP128to255
Rx 128- to 255-Byte Packets Statistic Register.
RmonRP256to511
Rx 256- to 511-Byte Packets Statistic Register.
RmonRP512to1023
Rx 512- to 1023-Byte Packets Statistic Register.
RmonRP1024to2047
Rx 1024- to 2047-Byte Packets Statistic Register.
RmonRPGte2048
Rx Packets Greater than 2048 Bytes Statistic Register.
RmonRPackets
Rx Packet Count Statistic Register.
RmonRUndersize
Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register.
RmonTBcPkt
Tx Broadcast Packets Statistic Register.
RmonTCol
Tx Collision Count Statistic Register.
RmonTCrcAlign
Tx Packets with CRC/Align Error Statistic Register.
RmonTFrag
Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register.
RmonTJab
Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register.
RmonTMcPkt
Tx Multicast Packets Statistic Register.
RmonTOctets
Tx Octets Statistic Register.
RmonTOversize
Tx Packets GT MAX_FL bytes and Good CRC Statistic Register.
RmonTP64
Tx 64-Byte Packets Statistic Register.
RmonTP65to127
Tx 65- to 127-byte Packets Statistic Register.
RmonTP128to255
Tx 128- to 255-byte Packets Statistic Register.
RmonTP256to511
Tx 256- to 511-byte Packets Statistic Register.
RmonTP512to1023
Tx 512- to 1023-byte Packets Statistic Register.
RmonTP1024to2047
Tx 1024- to 2047-byte Packets Statistic Register.
RmonTPGte2048
Tx Packets Greater Than 2048 Bytes Statistic Register.
RmonTPackets
Tx Packet Count Statistic Register.
RmonTUndersize
Tx Packets Less Than Bytes and Good CRC Statistic Register.
Rsem
Receive FIFO Section Empty Threshold.
Rsfl
Receive FIFO Section Full Threshold.
Rxic0
Receive Interrupt Coalescing Register.
Tacc
Transmit Accelerator Function Configuration.
Taem
Transmit FIFO Almost Empty Threshold.
Tafl
Transmit FIFO Almost Full Threshold.
Tccr0
Timer Compare Capture Register.
Tccr1
Timer Compare Capture Register.
Tccr2
Timer Compare Capture Register.
Tccr3
Timer Compare Capture Register.
Tcr
Transmit Control Register.
Tcsr0
Timer Control Status Register.
Tcsr1
Timer Control Status Register.
Tcsr2
Timer Control Status Register.
Tcsr3
Timer Control Status Register.
Tdar
Transmit Descriptor Active Register - Ring 0.
Tdsr
Transmit Buffer Descriptor Ring 0 Start Register.
Tfwr
Transmit FIFO Watermark Register.
Tgsr
Timer Global Status Register.
Tipg
Transmit Inter-Packet Gap.
Tsem
Transmit FIFO Section Empty Threshold.
Txic0
Transmit Interrupt Coalescing Register.