#[repr(u8)]pub enum Tcsr2Tmode {
Show 16 variants
TmrDis = 0,
TmrRe = 1,
TmrFe = 2,
TmrBe = 3,
TmrOut = 4,
TmrToggle = 5,
TmrClr = 6,
TmrSetOut = 7,
_RESERVED_8 = 8,
TmrClrSet1 = 9,
TmrClrSet = 10,
_RESERVED_b = 11,
_RESERVED_c = 12,
_RESERVED_d = 13,
TmrOutCmpLow = 14,
TmrOutCmpHigh = 15,
}Variants§
TmrDis = 0
Timer Channel is disabled.
TmrRe = 1
Timer Channel is configured for Input Capture on rising edge.
TmrFe = 2
Timer Channel is configured for Input Capture on falling edge.
TmrBe = 3
Timer Channel is configured for Input Capture on both edges.
TmrOut = 4
Timer Channel is configured for Output Compare - software only.
TmrToggle = 5
Timer Channel is configured for Output Compare - toggle output on compare.
TmrClr = 6
Timer Channel is configured for Output Compare - clear output on compare.
TmrSetOut = 7
Timer Channel is configured for Output Compare - set output on compare.
_RESERVED_8 = 8
TmrClrSet1 = 9
Timer Channel is configured for Output Compare - set output on compare, clear output on overflow.
TmrClrSet = 10
Timer Channel is configured for Output Compare - clear output on compare, set output on overflow.
_RESERVED_b = 11
_RESERVED_c = 12
_RESERVED_d = 13
TmrOutCmpLow = 14
Timer Channel is configured for Output Compare - pulse output low on compare for 1 to 32 1588-clock cycles as specified by TPWC.
TmrOutCmpHigh = 15
Timer Channel is configured for Output Compare - pulse output high on compare for 1 to 32 1588-clock cycles as specified by TPWC.
Implementations§
Source§impl Tcsr2Tmode
impl Tcsr2Tmode
Trait Implementations§
Source§impl Clone for Tcsr2Tmode
impl Clone for Tcsr2Tmode
Source§fn clone(&self) -> Tcsr2Tmode
fn clone(&self) -> Tcsr2Tmode
1.0.0 · Source§fn clone_from(&mut self, source: &Self)
fn clone_from(&mut self, source: &Self)
source. Read more