Struct Mcr0 

#[repr(transparent)]
pub struct Mcr0(pub u32);

Module Control Register 0

Tuple Fields

0: u32

Implementations

impl Mcr0

pub const fn swreset(&self) -> bool

Software Reset

pub const fn set_swreset(&mut self, val: bool)

Software Reset

pub const fn mdis(&self) -> bool

Module Disable

pub const fn set_mdis(&mut self, val: bool)

Module Disable

pub const fn rxclksrc(&self) -> Rxclksrc

Sample Clock source selection for Flash Reading

pub const fn set_rxclksrc(&mut self, val: Rxclksrc)

Sample Clock source selection for Flash Reading

pub const fn ardfen(&self) -> Ardfen

Enable AHB bus Read Access to IP RX FIFO.

pub const fn set_ardfen(&mut self, val: Ardfen)

Enable AHB bus Read Access to IP RX FIFO.

pub const fn atdfen(&self) -> Atdfen

Enable AHB bus Write Access to IP TX FIFO.

pub const fn set_atdfen(&mut self, val: Atdfen)

Enable AHB bus Write Access to IP TX FIFO.

pub const fn serclkdiv(&self) -> Serclkdiv

The serial root clock could be divided inside FlexSPI . See Clocks section for more details on clocking.

pub const fn set_serclkdiv(&mut self, val: Serclkdiv)

The serial root clock could be divided inside FlexSPI . See Clocks section for more details on clocking.

pub const fn hsen(&self) -> Hsen

Half Speed Serial Flash access Enable.

pub const fn set_hsen(&mut self, val: Hsen)

Half Speed Serial Flash access Enable.

pub const fn dozeen(&self) -> Dozeen

Doze mode enable bit

pub const fn set_dozeen(&mut self, val: Dozeen)

Doze mode enable bit

pub const fn combinationen(&self) -> bool

This bit is to support Flash Octal mode access by combining Port A and B Data pins (A_DATA[3:0] and B_DATA[3:0]), when Port A and Port B are of 4 bit data width.

pub const fn set_combinationen(&mut self, val: bool)

This bit is to support Flash Octal mode access by combining Port A and B Data pins (A_DATA[3:0] and B_DATA[3:0]), when Port A and Port B are of 4 bit data width.

pub const fn sckfreerunen(&self) -> bool

This bit is used to force SCLK output free-running. For FPGA applications, external device may use SCLK as reference clock to its internal PLL. If SCLK free-running is enabled, data sampling with loopback clock from SCLK pad is not supported (MCR0[RXCLKSRC]=2).

pub const fn set_sckfreerunen(&mut self, val: bool)

This bit is used to force SCLK output free-running. For FPGA applications, external device may use SCLK as reference clock to its internal PLL. If SCLK free-running is enabled, data sampling with loopback clock from SCLK pad is not supported (MCR0[RXCLKSRC]=2).

pub const fn ipgrantwait(&self) -> u8

Time out wait cycle for IP command grant.

pub const fn set_ipgrantwait(&mut self, val: u8)

Time out wait cycle for IP command grant.

pub const fn ahbgrantwait(&self) -> u8

Timeout wait cycle for AHB command grant.

pub const fn set_ahbgrantwait(&mut self, val: u8)

Timeout wait cycle for AHB command grant.

Trait Implementations

impl Clone for Mcr0

fn clone(&self) -> Mcr0

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for Mcr0

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Default for Mcr0

fn default() -> Mcr0

Returns the “default value” for a type.

impl PartialEq for Mcr0

fn eq(&self, other: &Mcr0) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Mcr0

impl Eq for Mcr0

impl StructuralPartialEq for Mcr0