Struct Vdctrl0Clr 

#[repr(transparent)]
pub struct Vdctrl0Clr(pub u32);

LCDIF VSYNC Mode and Dotclk Mode Control Register0

Tuple Fields

0: u32

Implementations

impl Vdctrl0Clr

pub const fn vsync_pulse_width(&self) -> u32

Number of units for which VSYNC signal is active

pub const fn set_vsync_pulse_width(&mut self, val: u32)

Number of units for which VSYNC signal is active

pub const fn half_line_mode(&self) -> bool

When this bit is 0, the first field (VSYNC period) will end in half a horizontal line and the second field will begin with half a horizontal line

pub const fn set_half_line_mode(&mut self, val: bool)

When this bit is 0, the first field (VSYNC period) will end in half a horizontal line and the second field will begin with half a horizontal line

pub const fn half_line(&self) -> bool

Setting this bit to 1 will make the total VSYNC period equal to the VSYNC_PERIOD field plus half the HORIZONTAL_PERIOD field (i

pub const fn set_half_line(&mut self, val: bool)

Setting this bit to 1 will make the total VSYNC period equal to the VSYNC_PERIOD field plus half the HORIZONTAL_PERIOD field (i

pub const fn vsync_pulse_width_unit(&self) -> bool

Default 0 for counting VSYNC_PULSE_WIDTH in terms of DISPLAY CLOCK (pix_clk) cycles

pub const fn set_vsync_pulse_width_unit(&mut self, val: bool)

Default 0 for counting VSYNC_PULSE_WIDTH in terms of DISPLAY CLOCK (pix_clk) cycles

pub const fn vsync_period_unit(&self) -> bool

Default 0 for counting VSYNC_PERIOD in terms of DISPLAY CLOCK (pix_clk) cycles

pub const fn set_vsync_period_unit(&mut self, val: bool)

Default 0 for counting VSYNC_PERIOD in terms of DISPLAY CLOCK (pix_clk) cycles

pub const fn enable_pol(&self) -> bool

Default 0 active low during valid data transfer on each horizontal line.

pub const fn set_enable_pol(&mut self, val: bool)

Default 0 active low during valid data transfer on each horizontal line.

pub const fn dotclk_pol(&self) -> bool

Default is data launched at negative edge of DOTCLK and captured at positive edge

pub const fn set_dotclk_pol(&mut self, val: bool)

Default is data launched at negative edge of DOTCLK and captured at positive edge

pub const fn hsync_pol(&self) -> bool

Default 0 active low during HSYNC_PULSE_WIDTH time and will be high during the rest of the HSYNC period

pub const fn set_hsync_pol(&mut self, val: bool)

Default 0 active low during HSYNC_PULSE_WIDTH time and will be high during the rest of the HSYNC period

pub const fn vsync_pol(&self) -> bool

Default 0 active low during VSYNC_PULSE_WIDTH time and will be high during the rest of the VSYNC period

pub const fn set_vsync_pol(&mut self, val: bool)

Default 0 active low during VSYNC_PULSE_WIDTH time and will be high during the rest of the VSYNC period

pub const fn enable_present(&self) -> bool

Setting this bit to 1 will make the hardware generate the ENABLE signal in the DOTCLK mode, thereby making it the true RGB interface along with the remaining three signals VSYNC, HSYNC and DOTCLK

pub const fn set_enable_present(&mut self, val: bool)

Setting this bit to 1 will make the hardware generate the ENABLE signal in the DOTCLK mode, thereby making it the true RGB interface along with the remaining three signals VSYNC, HSYNC and DOTCLK

Trait Implementations

impl Clone for Vdctrl0Clr

fn clone(&self) -> Vdctrl0Clr

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for Vdctrl0Clr

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Default for Vdctrl0Clr

fn default() -> Vdctrl0Clr

Returns the “default value” for a type.

impl PartialEq for Vdctrl0Clr

fn eq(&self, other: &Vdctrl0Clr) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Vdctrl0Clr

impl Eq for Vdctrl0Clr

impl StructuralPartialEq for Vdctrl0Clr