Module regs 

Structs

Ccr

Clock Configuration

Cfgr0

Configuration 0

Cfgr1

Configuration 1

Cr

Control

Der

DMA Enable

Dmr0

Data Match 0

Dmr1

Data Match 1

Fcr

FIFO Control

Fsr

FIFO Status

Ier

Interrupt Enable

Param

Parameter

Rdr

Receive Data

Rsr

Receive Status

Sr

Status

Tcr

Transmit Command

Tdr

Transmit Data

Verid

Version ID