#[repr(transparent)]pub struct Sis(pub u32);Expand description
InterruptStat Register
Tuple Fields§
§0: u32Implementations§
Source§impl Sis
impl Sis
Sourcepub const fn rx_fifoful(&self) -> bool
pub const fn rx_fifoful(&self) -> bool
SPDIF Rx FIFO full, can’t be cleared with reg. IntClear. To clear it, read from Rx FIFO.
Sourcepub const fn set_rx_fifoful(&mut self, val: bool)
pub const fn set_rx_fifoful(&mut self, val: bool)
SPDIF Rx FIFO full, can’t be cleared with reg. IntClear. To clear it, read from Rx FIFO.
Sourcepub const fn tx_em(&self) -> bool
pub const fn tx_em(&self) -> bool
SPDIF Tx FIFO empty, can’t be cleared with reg. IntClear. To clear it, write toTx FIFO.
Sourcepub const fn set_tx_em(&mut self, val: bool)
pub const fn set_tx_em(&mut self, val: bool)
SPDIF Tx FIFO empty, can’t be cleared with reg. IntClear. To clear it, write toTx FIFO.
Sourcepub const fn set_lock_loss(&mut self, val: bool)
pub const fn set_lock_loss(&mut self, val: bool)
SPDIF receiver loss of lock
Sourcepub const fn rx_fiforesyn(&self) -> bool
pub const fn rx_fiforesyn(&self) -> bool
Rx FIFO resync
Sourcepub const fn set_rx_fiforesyn(&mut self, val: bool)
pub const fn set_rx_fiforesyn(&mut self, val: bool)
Rx FIFO resync
Sourcepub const fn rx_fifoun_ov(&self) -> bool
pub const fn rx_fifoun_ov(&self) -> bool
Rx FIFO underrun/overrun
Sourcepub const fn set_rx_fifoun_ov(&mut self, val: bool)
pub const fn set_rx_fifoun_ov(&mut self, val: bool)
Rx FIFO underrun/overrun
Sourcepub const fn set_uqsync(&mut self, val: bool)
pub const fn set_uqsync(&mut self, val: bool)
U/Q Channel sync found
Sourcepub const fn set_qrx_ov(&mut self, val: bool)
pub const fn set_qrx_ov(&mut self, val: bool)
Q Channel receive register overrun
Sourcepub const fn set_qrx_ful(&mut self, val: bool)
pub const fn set_qrx_ful(&mut self, val: bool)
Q Channel receive register full, can’t be cleared with reg
Sourcepub const fn set_urx_ov(&mut self, val: bool)
pub const fn set_urx_ov(&mut self, val: bool)
U Channel receive register overrun
Sourcepub const fn set_urx_ful(&mut self, val: bool)
pub const fn set_urx_ful(&mut self, val: bool)
U Channel receive register full, can’t be cleared with reg
Sourcepub const fn set_bit_err(&mut self, val: bool)
pub const fn set_bit_err(&mut self, val: bool)
SPDIF receiver found parity bit error
Sourcepub const fn set_sym_err(&mut self, val: bool)
pub const fn set_sym_err(&mut self, val: bool)
SPDIF receiver found illegal symbol
Sourcepub const fn val_no_good(&self) -> bool
pub const fn val_no_good(&self) -> bool
SPDIF validity flag no good
Sourcepub const fn set_val_no_good(&mut self, val: bool)
pub const fn set_val_no_good(&mut self, val: bool)
SPDIF validity flag no good
Sourcepub const fn set_tx_resyn(&mut self, val: bool)
pub const fn set_tx_resyn(&mut self, val: bool)
SPDIF Tx FIFO resync
Sourcepub const fn set_tx_un_ov(&mut self, val: bool)
pub const fn set_tx_un_ov(&mut self, val: bool)
SPDIF Tx FIFO under/overrun