Struct Clkctl0 

pub struct Clkctl0 { /* private fields */ }

clock ccontroller 0

Implementations

impl Clkctl0

pub const unsafe fn from_ptr(ptr: *mut ()) -> Self

pub const fn as_ptr(&self) -> *mut ()

pub const fn pscctl0(self) -> Reg<Pscctl0, RW>

clock control register 0

pub const fn pscctl1(self) -> Reg<Pscctl1, RW>

clock control register 1

pub const fn pscctl2(self) -> Reg<Pscctl2, RW>

clock control register 2

pub const fn pscctl0_set(self) -> Reg<Pscctl0Set, W>

clock set register 0

pub const fn pscctl1_set(self) -> Reg<Pscctl1Set, W>

clock set register 1

pub const fn pscctl2_set(self) -> Reg<Pscctl2Set, W>

clock set register 2

pub const fn pscctl0_clr(self) -> Reg<Pscctl0Clr, W>

clock clear register 0

pub const fn pscctl1_clr(self) -> Reg<Pscctl1Clr, W>

clock clear register 1

pub const fn pscctl2_clr(self) -> Reg<Pscctl2Clr, W>

clock clear register 2

pub const fn ffroctl0(self) -> Reg<Ffroctl0, RW>

FFRO control 0

pub const fn ffroctl1(self) -> Reg<Ffroctl1, RW>

FFRO control 1

pub const fn sysoscctl0(self) -> Reg<Sysoscctl0, RW>

system oscillator control 0

pub const fn sysoscbypass(self) -> Reg<Sysoscbypass, RW>

system oscillator bypass

pub const fn lposcctl0(self) -> Reg<Lposcctl0, RW>

low power oscillator control 0

pub const fn osc32khzctl0(self) -> Reg<Osc32khzctl0, RW>

32k oscillator control0

pub const fn syspll0clksel(self) -> Reg<Syspll0clksel, RW>

system pll0 clock selection

pub const fn syspll0ctl0(self) -> Reg<Syspll0ctl0, RW>

system pll0 control0

pub const fn syspll0locktimediv2(self) -> Reg<Syspll0locktimediv2, RW>

system pll0 lock time

pub const fn syspll0num(self) -> Reg<Syspll0num, RW>

system pll0 number

pub const fn syspll0denom(self) -> Reg<Syspll0denom, RW>

system pll0 denom

pub const fn syspll0pfd(self) -> Reg<Syspll0pfd, RW>

sys pll0 PFD

pub const fn mainpllclkdiv(self) -> Reg<Mainpllclkdiv, RW>

main pll clk divider

pub const fn dsppllclkdiv(self) -> Reg<Dsppllclkdiv, RW>

dsp pll clk divider

pub const fn aux0pllclkdiv(self) -> Reg<Aux0pllclkdiv, RW>

aux0 pll clk divider

pub const fn aux1pllclkdiv(self) -> Reg<Aux1pllclkdiv, RW>

aux1 pll clk divider

pub const fn syscpuahbclkdiv(self) -> Reg<Syscpuahbclkdiv, RW>

system cpu AHB clock divider

pub const fn mainclksela(self) -> Reg<Mainclksela, RW>

main clock selection A

pub const fn mainclkselb(self) -> Reg<Mainclkselb, RW>

main clock selection B

pub const fn pfcdiv(self, n: usize) -> Reg<Pfcdiv, RW>

PFC divider register N

pub const fn flexspifclksel(self) -> Reg<Flexspifclksel, RW>

FlexSPI FCLK selection

pub const fn flexspifclkdiv(self) -> Reg<Flexspifclkdiv, RW>

FlexSPI FCLK divider

pub const fn sctfclksel(self) -> Reg<Sctfclksel, RW>

SCT FCLK selection

pub const fn sctfclkdiv(self) -> Reg<Sctfclkdiv, RW>

SCT fclk divider

pub const fn usbhsfclksel(self) -> Reg<Usbhsfclksel, RW>

USBHS Fclk selection

pub const fn usbhsfclkdiv(self) -> Reg<Usbhsfclkdiv, RW>

USBHS Fclk divider

pub const fn sdio0fclksel(self) -> Reg<Sdio0fclksel, RW>

SDIO0 FCLK selection

pub const fn sdio0fclkdiv(self) -> Reg<Sdio0fclkdiv, RW>

SDIO0 FCLK divider

pub const fn sdio1fclksel(self) -> Reg<Sdio1fclksel, RW>

SDIO1 FCLK selection

pub const fn sdio1fclkdiv(self) -> Reg<Sdio1fclkdiv, RW>

SDIO1 FCLK divider

pub const fn espifclksel0(self) -> Reg<Espifclksel0, RW>

ESPI clock selection

pub const fn adc0fclksel0(self) -> Reg<Adc0fclksel0, RW>

ADC0 fclk selection 0

pub const fn adc0fclksel1(self) -> Reg<Adc0fclksel1, RW>

ADC0 fclk selection 1

pub const fn adc0fclkdiv(self) -> Reg<Adc0fclkdiv, RW>

ADC0 fclk divider

pub const fn utickfclksel(self) -> Reg<Utickfclksel, RW>

UTICK fclk selection

pub const fn wdt0fclksel(self) -> Reg<Wdt0fclksel, RW>

wdt clock selection

pub const fn wakeclk32khzsel(self) -> Reg<Wakeclk32khzsel, RW>

32k wake clock selection

pub const fn wakeclk32khzdiv(self) -> Reg<Wakeclk32khzdiv, RW>

32k wake clock divider

pub const fn systickfclksel(self) -> Reg<Systickfclksel, RW>

system tick fclk selection

pub const fn systickfclkdiv(self) -> Reg<Systickfclkdiv, RW>

system tick fclk divider

Trait Implementations

impl Clone for Clkctl0

fn clone(&self) -> Clkctl0

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl PartialEq for Clkctl0

fn eq(&self, other: &Clkctl0) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Clkctl0

impl Eq for Clkctl0

impl Send for Clkctl0

impl StructuralPartialEq for Clkctl0

impl Sync for Clkctl0