#[repr(transparent)]pub struct Audiopll0pfd(pub u32);Expand description
audio pll0 PFD
Tuple Fields§
§0: u32Implementations§
Source§impl Audiopll0pfd
impl Audiopll0pfd
Sourcepub const fn pfd0(&self) -> u8
pub const fn pfd0(&self) -> u8
PLL Fractional Divider 0: Controls the fractional divider value. Valid PFD values are decimal 12-35.
Sourcepub const fn set_pfd0(&mut self, val: u8)
pub const fn set_pfd0(&mut self, val: u8)
PLL Fractional Divider 0: Controls the fractional divider value. Valid PFD values are decimal 12-35.
Sourcepub const fn pfd0_clkrdy(&self) -> bool
pub const fn pfd0_clkrdy(&self) -> bool
PFD0 Clock Ready Status Flag: Read as 1 clock ready. Cleared by writing a 1.
Sourcepub const fn set_pfd0_clkrdy(&mut self, val: bool)
pub const fn set_pfd0_clkrdy(&mut self, val: bool)
PFD0 Clock Ready Status Flag: Read as 1 clock ready. Cleared by writing a 1.
Sourcepub const fn pfd0_clkgate(&self) -> bool
pub const fn pfd0_clkgate(&self) -> bool
PFD0 Clock Gate: 0: PFD0 clock is not gated. 1: PFD0 clock is gated
Sourcepub const fn set_pfd0_clkgate(&mut self, val: bool)
pub const fn set_pfd0_clkgate(&mut self, val: bool)
PFD0 Clock Gate: 0: PFD0 clock is not gated. 1: PFD0 clock is gated
Sourcepub const fn pfd1(&self) -> u8
pub const fn pfd1(&self) -> u8
PLL Fractional Divider 1: Controls the fractional divider value. Valid PFD values are decimal 12-35.
Sourcepub const fn set_pfd1(&mut self, val: u8)
pub const fn set_pfd1(&mut self, val: u8)
PLL Fractional Divider 1: Controls the fractional divider value. Valid PFD values are decimal 12-35.
Sourcepub const fn pfd1_clkrdy(&self) -> bool
pub const fn pfd1_clkrdy(&self) -> bool
PFD1 Clock Ready Status Flag: Read as 1 clock ready. Cleared by writing a 1.
Sourcepub const fn set_pfd1_clkrdy(&mut self, val: bool)
pub const fn set_pfd1_clkrdy(&mut self, val: bool)
PFD1 Clock Ready Status Flag: Read as 1 clock ready. Cleared by writing a 1.
Sourcepub const fn pfd1_clkgate(&self) -> bool
pub const fn pfd1_clkgate(&self) -> bool
PFD1 Clock Gate: 0: PFD1 clock is not gated. 1: PFD1 clock is gated.
Sourcepub const fn set_pfd1_clkgate(&mut self, val: bool)
pub const fn set_pfd1_clkgate(&mut self, val: bool)
PFD1 Clock Gate: 0: PFD1 clock is not gated. 1: PFD1 clock is gated.
Sourcepub const fn pfd2(&self) -> u8
pub const fn pfd2(&self) -> u8
PLL Fractional Divider 2: Controls the fractional divider value. Valid PFD values are decimal 12-35.
Sourcepub const fn set_pfd2(&mut self, val: u8)
pub const fn set_pfd2(&mut self, val: u8)
PLL Fractional Divider 2: Controls the fractional divider value. Valid PFD values are decimal 12-35.
Sourcepub const fn pfd2_clkrdy(&self) -> bool
pub const fn pfd2_clkrdy(&self) -> bool
PFD2 Clock Ready Status Flag: Read as 1 clock ready. Cleared by writing a 1.
Sourcepub const fn set_pfd2_clkrdy(&mut self, val: bool)
pub const fn set_pfd2_clkrdy(&mut self, val: bool)
PFD2 Clock Ready Status Flag: Read as 1 clock ready. Cleared by writing a 1.
Sourcepub const fn pfd2_clkgate(&self) -> bool
pub const fn pfd2_clkgate(&self) -> bool
PFD2 Clock Gate: 0: PFD2 clock is not gated. 1: PFD2 clock is gated.
Sourcepub const fn set_pfd2_clkgate(&mut self, val: bool)
pub const fn set_pfd2_clkgate(&mut self, val: bool)
PFD2 Clock Gate: 0: PFD2 clock is not gated. 1: PFD2 clock is gated.
Sourcepub const fn pfd3(&self) -> u8
pub const fn pfd3(&self) -> u8
PLL Fractional Divider 3: Controls the fractional divider value. Valid PFD values are decimal 12-35.
Sourcepub const fn set_pfd3(&mut self, val: u8)
pub const fn set_pfd3(&mut self, val: u8)
PLL Fractional Divider 3: Controls the fractional divider value. Valid PFD values are decimal 12-35.
Sourcepub const fn pfd3_clkrdy(&self) -> bool
pub const fn pfd3_clkrdy(&self) -> bool
PFD3 Clock Ready Status Flag: Read as 1 clock ready. Cleared by writing a 1.
Sourcepub const fn set_pfd3_clkrdy(&mut self, val: bool)
pub const fn set_pfd3_clkrdy(&mut self, val: bool)
PFD3 Clock Ready Status Flag: Read as 1 clock ready. Cleared by writing a 1.
Sourcepub const fn pfd3_clkgate(&self) -> bool
pub const fn pfd3_clkgate(&self) -> bool
PFD3 Clock Gate: 0: PFD3 clock is not gated. 1: PFD3 clock is gated.
Sourcepub const fn set_pfd3_clkgate(&mut self, val: bool)
pub const fn set_pfd3_clkgate(&mut self, val: bool)
PFD3 Clock Gate: 0: PFD3 clock is not gated. 1: PFD3 clock is gated.
Trait Implementations§
Source§impl Clone for Audiopll0pfd
impl Clone for Audiopll0pfd
Source§fn clone(&self) -> Audiopll0pfd
fn clone(&self) -> Audiopll0pfd
1.0.0 · Source§fn clone_from(&mut self, source: &Self)
fn clone_from(&mut self, source: &Self)
source. Read more