Struct Ctimer

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pub struct Ctimer { /* private fields */ }

Expand description

LPC-Next0 Standard async counter/timer

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pub const fn ir(self) -> Reg<Ir, RW>

Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending.

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pub const fn tcr(self) -> Reg<Tcr, RW>

Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR.

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pub const fn tc(self) -> Reg<Tc, RW>

Timer Counter. The 32 bit TC is incremented every PR+1 cycles of the APB bus clock. The TC is controlled through the TCR.

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pub const fn pr(self) -> Reg<Pr, RW>

Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC.

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pub const fn pc(self) -> Reg<Pc, RW>

Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface.

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pub const fn mcr(self) -> Reg<Mcr, RW>

Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs.

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pub const fn mr(self, n: usize) -> Reg<Mr, RW>

Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.

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pub const fn ccr(self) -> Reg<Ccr, RW>

Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place.

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pub const fn cr(self, n: usize) -> Reg<Cr, R>

Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input.

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pub const fn emr(self) -> Reg<Emr, RW>

External Match Register. The EMR controls the match function and the external match pins.

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pub const fn ctcr(self) -> Reg<Ctcr, RW>

Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.

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pub const fn pwmc(self) -> Reg<Pwmc, RW>

PWM Control Register. The PWMCON enables PWM mode for the external match pins.

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pub const fn msr(self, n: usize) -> Reg<Msr, RW>

Match Shadow Register . If enabled, the Match Register will be automatically reloaded with the contents of this register whenever the TC is reset to zero.