Struct Dma 

pub struct Dma { /* private fields */ }

LPC-Next0 DMA controller

Implementations

impl Dma

pub const unsafe fn from_ptr(ptr: *mut ()) -> Self

pub const fn as_ptr(&self) -> *mut ()

pub const fn ctrl(self) -> Reg<Ctrl, RW>

DMA control.

pub const fn intstat(self) -> Reg<Intstat, R>

Interrupt status.

pub const fn srambase(self) -> Reg<Srambase, RW>

SRAM address of the channel configuration table.

pub const fn enableset0(self) -> Reg<Enableset0, RW>

Channel Enable read and Set for all DMA channels.

pub const fn enableset1(self) -> Reg<Enableset1, RW>

Channel Enable read and Set for all DMA channels.

pub const fn enableclr0(self) -> Reg<Enableclr0, W>

Channel Enable Clear for all DMA channels.

pub const fn enableclr1(self) -> Reg<Enableclr1, W>

Channel Enable Clear for all DMA channels.

pub const fn active0(self) -> Reg<Active0, R>

Channel Active status for all DMA channels.

pub const fn active1(self) -> Reg<Active1, R>

Channel Active status for all DMA channels.

pub const fn busy0(self) -> Reg<Busy0, R>

Channel Busy status for all DMA channels.

pub const fn busy1(self) -> Reg<Busy1, R>

Channel Busy status for all DMA channels.

pub const fn errint0(self) -> Reg<Errint0, RW>

Error Interrupt status for all DMA channels.

pub const fn errint1(self) -> Reg<Errint1, RW>

Error Interrupt status for all DMA channels.

pub const fn intenset0(self) -> Reg<Intenset0, RW>

Interrupt Enable read and Set for all DMA channels.

pub const fn intenset1(self) -> Reg<Intenset1, RW>

Interrupt Enable read and Set for all DMA channels.

pub const fn intenclr0(self) -> Reg<Intenclr0, W>

Interrupt Enable Clear for all DMA channels.

pub const fn intenclr1(self) -> Reg<Intenclr1, W>

Interrupt Enable Clear for all DMA channels.

pub const fn inta0(self) -> Reg<Inta0, RW>

Interrupt A status for all DMA channels.

pub const fn inta1(self) -> Reg<Inta1, RW>

Interrupt A status for all DMA channels.

pub const fn intb0(self) -> Reg<Intb0, RW>

Interrupt B status for all DMA channels.

pub const fn intb1(self) -> Reg<Intb1, RW>

Interrupt B status for all DMA channels.

pub const fn setvalid0(self) -> Reg<Setvalid0, W>

Set ValidPending control bits for all DMA channels.

pub const fn setvalid1(self) -> Reg<Setvalid1, W>

Set ValidPending control bits for all DMA channels.

pub const fn settrig0(self) -> Reg<Settrig0, W>

Set Trigger control bits for all DMA channels.

pub const fn settrig1(self) -> Reg<Settrig1, W>

Set Trigger control bits for all DMA channels.

pub const fn abort0(self) -> Reg<Abort0, W>

Channel Abort control for all DMA channels.

pub const fn abort1(self) -> Reg<Abort1, W>

Channel Abort control for all DMA channels.

pub const fn channel(self, n: usize) -> Channel

Array of registers: CFG, CTLSTAT, XFERCFG

Trait Implementations

impl Clone for Dma

fn clone(&self) -> Dma

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl PartialEq for Dma

fn eq(&self, other: &Dma) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Dma

impl Eq for Dma

impl Send for Dma

impl StructuralPartialEq for Dma

impl Sync for Dma