#[repr(transparent)]pub struct Mstat(pub u32);Expand description
Master Status of whole peripheral
Tuple Fields§
§0: u32Implementations§
Source§impl Mstat
impl Mstat
Sourcepub const fn set_port_int(&mut self, val: u8)
pub const fn set_port_int(&mut self, val: u8)
Corresponding port is pending interrupt service
Sourcepub const fn set_p80int(&mut self, val: bool)
pub const fn set_p80int(&mut self, val: bool)
Port80 has had a request and is pending service.
Sourcepub const fn set_bus_rst(&mut self, val: bool)
pub const fn set_bus_rst(&mut self, val: bool)
If 1, the entered or left reset. Sticky - must clear.
Sourcepub const fn irq_upd(&self) -> bool
pub const fn irq_upd(&self) -> bool
If 1, the bus had an IRQ update completion (for eSPI, IRQPush done; for LPC, SERIRQ done)
Sourcepub const fn set_irq_upd(&mut self, val: bool)
pub const fn set_irq_upd(&mut self, val: bool)
If 1, the bus had an IRQ update completion (for eSPI, IRQPush done; for LPC, SERIRQ done)
Sourcepub const fn wire_chg(&self) -> bool
pub const fn wire_chg(&self) -> bool
If 1, one or more input VWire has changed since last cleared for eSPI; for LPC, SERIRQ started
Sourcepub const fn set_wire_chg(&mut self, val: bool)
pub const fn set_wire_chg(&mut self, val: bool)
If 1, one or more input VWire has changed since last cleared for eSPI; for LPC, SERIRQ started
Sourcepub const fn hstall(&self) -> bool
pub const fn hstall(&self) -> bool
If 1, the Host is stalled on a read from or write to a port that has the StallRd or StallWr bit set in the PnCFG register
Sourcepub const fn set_hstall(&mut self, val: bool)
pub const fn set_hstall(&mut self, val: bool)
If 1, the Host is stalled on a read from or write to a port that has the StallRd or StallWr bit set in the PnCFG register
Sourcepub const fn crcerr(&self) -> bool
pub const fn crcerr(&self) -> bool
If 1, the CRC from the Master did not match the computed CRC
Sourcepub const fn set_crcerr(&mut self, val: bool)
pub const fn set_crcerr(&mut self, val: bool)
If 1, the CRC from the Master did not match the computed CRC
Sourcepub const fn set_in_rst(&mut self, val: bool)
pub const fn set_in_rst(&mut self, val: bool)
If 1, the bus in reset.
Sourcepub const fn comp_pend(&self) -> bool
pub const fn comp_pend(&self) -> bool
If 1, completions are pending for eSPI; indicates quiet mode for LPC.
Sourcepub const fn set_comp_pend(&mut self, val: bool)
pub const fn set_comp_pend(&mut self, val: bool)
If 1, completions are pending for eSPI; indicates quiet mode for LPC.
Sourcepub const fn set_mast_pend(&mut self, val: bool)
pub const fn set_mast_pend(&mut self, val: bool)
If 1, Mastering is pending (flash or memory)
Sourcepub const fn alert_pend(&self) -> bool
pub const fn alert_pend(&self) -> bool
If 1, the Alert request pin is pending (whether separate pin or MISO)
Sourcepub const fn set_alert_pend(&mut self, val: bool)
pub const fn set_alert_pend(&mut self, val: bool)
If 1, the Alert request pin is pending (whether separate pin or MISO)