Struct Mcr2 

#[repr(transparent)]
pub struct Mcr2(pub u32);

Module Control Register 2

Tuple Fields

0: u32

Implementations

impl Mcr2

pub const fn clrahbbufopt(&self) -> Clrahbbufopt

This bit determines whether AHB RX Buffer and AHB TX Buffer will be cleaned automatically when FlexSPI returns STOP mode ACK. Software should set this bit if AHB RX Buffer or AHB TX Buffer will be powered off in STOP mode. Otherwise AHB read access after exiting STOP mode may hit AHB RX Buffer or AHB TX Buffer but their data entries are invalid.

pub const fn set_clrahbbufopt(&mut self, val: Clrahbbufopt)

This bit determines whether AHB RX Buffer and AHB TX Buffer will be cleaned automatically when FlexSPI returns STOP mode ACK. Software should set this bit if AHB RX Buffer or AHB TX Buffer will be powered off in STOP mode. Otherwise AHB read access after exiting STOP mode may hit AHB RX Buffer or AHB TX Buffer but their data entries are invalid.

pub const fn clrlearnphase(&self) -> bool

The sampling clock phase selection will be reset to phase 0 when this bit is written with 0x1. This bit will be auto-cleared immediately.

pub const fn set_clrlearnphase(&mut self, val: bool)

The sampling clock phase selection will be reset to phase 0 when this bit is written with 0x1. This bit will be auto-cleared immediately.

pub const fn samedeviceen(&self) -> Samedeviceen

All external devices are same devices (both in types and size) for A1/A2/B1/B2.

pub const fn set_samedeviceen(&mut self, val: Samedeviceen)

All external devices are same devices (both in types and size) for A1/A2/B1/B2.

pub const fn sckbdiffopt(&self) -> Sckbdiffopt

B_SCLK pad can be used as A_SCLK differential clock output (inverted clock to A_SCLK). In this case, port B flash access is not available. After changing the value of this field, MCR0[SWRESET] should be set.

pub const fn set_sckbdiffopt(&mut self, val: Sckbdiffopt)

B_SCLK pad can be used as A_SCLK differential clock output (inverted clock to A_SCLK). In this case, port B flash access is not available. After changing the value of this field, MCR0[SWRESET] should be set.

pub const fn resumewait(&self) -> u8

Wait cycle (in AHB clock cycle) for idle state before suspended command sequence resumed.

pub const fn set_resumewait(&mut self, val: u8)

Wait cycle (in AHB clock cycle) for idle state before suspended command sequence resumed.

Trait Implementations

impl Clone for Mcr2

fn clone(&self) -> Mcr2

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for Mcr2

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Default for Mcr2

fn default() -> Mcr2

Returns the “default value” for a type.

impl PartialEq for Mcr2

fn eq(&self, other: &Mcr2) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Mcr2

impl Eq for Mcr2

impl StructuralPartialEq for Mcr2