Struct Sts0 

#[repr(transparent)]
pub struct Sts0(pub u32);

Status Register 0

Tuple Fields

0: u32

Implementations

impl Sts0

pub const fn seqidle(&self) -> bool

This status bit indicates the state machine in SEQ_CTL is idle and there is command sequence executing on FlexSPI interface.

pub const fn set_seqidle(&mut self, val: bool)

This status bit indicates the state machine in SEQ_CTL is idle and there is command sequence executing on FlexSPI interface.

pub const fn arbidle(&self) -> bool

This status bit indicates the state machine in ARB_CTL is busy and there is command sequence granted by arbitrator and not finished yet on FlexSPI interface. When ARB_CTL state (ARBIDLE=0x1) is idle, there will be no transaction on FlexSPI interface also (SEQIDLE=0x1). So this bit should be polled to wait for FlexSPI controller become idle instead of SEQIDLE.

pub const fn set_arbidle(&mut self, val: bool)

This status bit indicates the state machine in ARB_CTL is busy and there is command sequence granted by arbitrator and not finished yet on FlexSPI interface. When ARB_CTL state (ARBIDLE=0x1) is idle, there will be no transaction on FlexSPI interface also (SEQIDLE=0x1). So this bit should be polled to wait for FlexSPI controller become idle instead of SEQIDLE.

pub const fn arbcmdsrc(&self) -> Arbcmdsrc

This status field indicates the trigger source of current command sequence granted by arbitrator. This field value is meaningless when ARB_CTL is not busy (STS0[ARBIDLE]=0x1).

pub const fn set_arbcmdsrc(&mut self, val: Arbcmdsrc)

This status field indicates the trigger source of current command sequence granted by arbitrator. This field value is meaningless when ARB_CTL is not busy (STS0[ARBIDLE]=0x1).

pub const fn datalearnphasea(&self) -> u8

Indicate the sampling clock phase selection on Port A after Data Learning.

pub const fn set_datalearnphasea(&mut self, val: u8)

Indicate the sampling clock phase selection on Port A after Data Learning.

pub const fn datalearnphaseb(&self) -> u8

Indicate the sampling clock phase selection on Port B after Data Learning.

pub const fn set_datalearnphaseb(&mut self, val: u8)

Indicate the sampling clock phase selection on Port B after Data Learning.

Trait Implementations

impl Clone for Sts0

fn clone(&self) -> Sts0

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for Sts0

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Default for Sts0

fn default() -> Sts0

Returns the “default value” for a type.

impl PartialEq for Sts0

fn eq(&self, other: &Sts0) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Sts0

impl Eq for Sts0

impl StructuralPartialEq for Sts0