Struct Dmac1ItrigEna0Clr 

#[repr(transparent)]
pub struct Dmac1ItrigEna0Clr(pub u32);

DMAC1 input trigger enable clear 0

Tuple Fields

0: u32

Implementations

impl Dmac1ItrigEna0Clr

pub const fn dmac1_itrig_inmux0(&self) -> Dmac1ItrigEna0ClrDmac1ItrigInmux0

DMAC1 input trigger inmux 0 enable clear

pub const fn set_dmac1_itrig_inmux0( &mut self, val: Dmac1ItrigEna0ClrDmac1ItrigInmux0, )

DMAC1 input trigger inmux 0 enable clear

pub const fn dmac1_itrig_inmux1(&self) -> Dmac1ItrigEna0ClrDmac1ItrigInmux1

DMAC1 input trigger inmux 1 enable clear

pub const fn set_dmac1_itrig_inmux1( &mut self, val: Dmac1ItrigEna0ClrDmac1ItrigInmux1, )

DMAC1 input trigger inmux 1 enable clear

pub const fn dmac1_itrig_inmux2(&self) -> bool

DMAC1 input trigger inmux 2 enable clear

pub const fn set_dmac1_itrig_inmux2(&mut self, val: bool)

DMAC1 input trigger inmux 2 enable clear

pub const fn dmac1_itrig_inmux3(&self) -> Dmac1ItrigEna0ClrDmac1ItrigInmux3

DMAC1 input trigger inmux 3 enable clear

pub const fn set_dmac1_itrig_inmux3( &mut self, val: Dmac1ItrigEna0ClrDmac1ItrigInmux3, )

DMAC1 input trigger inmux 3 enable clear

pub const fn dmac1_itrig_inmux4(&self) -> Dmac1ItrigEna0ClrDmac1ItrigInmux4

DMAC1 input trigger inmux 4 enable clear

pub const fn set_dmac1_itrig_inmux4( &mut self, val: Dmac1ItrigEna0ClrDmac1ItrigInmux4, )

DMAC1 input trigger inmux 4 enable clear

pub const fn dmac1_itrig_inmux5(&self) -> Dmac1ItrigEna0ClrDmac1ItrigInmux5

DMAC1 input trigger inmux 5 enable clear

pub const fn set_dmac1_itrig_inmux5( &mut self, val: Dmac1ItrigEna0ClrDmac1ItrigInmux5, )

DMAC1 input trigger inmux 5 enable clear

pub const fn dmac1_itrig_inmux6(&self) -> Dmac1ItrigEna0ClrDmac1ItrigInmux6

DMAC1 input trigger inmux 6 enable clear

pub const fn set_dmac1_itrig_inmux6( &mut self, val: Dmac1ItrigEna0ClrDmac1ItrigInmux6, )

DMAC1 input trigger inmux 6 enable clear

pub const fn dmac1_itrig_inmux7(&self) -> Dmac1ItrigEna0ClrDmac1ItrigInmux7

DMAC1 input trigger inmux 7 enable clear

pub const fn set_dmac1_itrig_inmux7( &mut self, val: Dmac1ItrigEna0ClrDmac1ItrigInmux7, )

DMAC1 input trigger inmux 7 enable clear

pub const fn dmac1_itrig_inmux8(&self) -> Dmac1ItrigEna0ClrDmac1ItrigInmux8

DMAC1 input trigger inmux 8 enable clear

pub const fn set_dmac1_itrig_inmux8( &mut self, val: Dmac1ItrigEna0ClrDmac1ItrigInmux8, )

DMAC1 input trigger inmux 8 enable clear

pub const fn dmac1_itrig_inmux9(&self) -> Dmac1ItrigEna0ClrDmac1ItrigInmux9

DMAC1 input trigger inmux 9 enable clear

pub const fn set_dmac1_itrig_inmux9( &mut self, val: Dmac1ItrigEna0ClrDmac1ItrigInmux9, )

DMAC1 input trigger inmux 9 enable clear

pub const fn dmac1_itrig_inmux10(&self) -> Dmac1ItrigEna0ClrDmac1ItrigInmux10

DMAC1 input trigger inmux 10 enable clear

pub const fn set_dmac1_itrig_inmux10( &mut self, val: Dmac1ItrigEna0ClrDmac1ItrigInmux10, )

DMAC1 input trigger inmux 10 enable clear

pub const fn dmac1_itrig_inmux11(&self) -> Dmac1ItrigEna0ClrDmac1ItrigInmux11

DMAC1 input trigger inmux 11 enable clear

pub const fn set_dmac1_itrig_inmux11( &mut self, val: Dmac1ItrigEna0ClrDmac1ItrigInmux11, )

DMAC1 input trigger inmux 11 enable clear

pub const fn dmac1_itrig_inmux12(&self) -> Dmac1ItrigEna0ClrDmac1ItrigInmux12

DMAC1 input trigger inmux 12 enable clear

pub const fn set_dmac1_itrig_inmux12( &mut self, val: Dmac1ItrigEna0ClrDmac1ItrigInmux12, )

DMAC1 input trigger inmux 12 enable clear

pub const fn dmac1_itrig_inmux13(&self) -> Dmac1ItrigEna0ClrDmac1ItrigInmux13

DMAC1 input trigger inmux 13 enable clear

pub const fn set_dmac1_itrig_inmux13( &mut self, val: Dmac1ItrigEna0ClrDmac1ItrigInmux13, )

DMAC1 input trigger inmux 13 enable clear

pub const fn dmac1_itrig_inmux14(&self) -> Dmac1ItrigEna0ClrDmac1ItrigInmux14

DMAC1 input trigger inmux 14 enable clear

pub const fn set_dmac1_itrig_inmux14( &mut self, val: Dmac1ItrigEna0ClrDmac1ItrigInmux14, )

DMAC1 input trigger inmux 14 enable clear

pub const fn dmac1_itrig_inmux15(&self) -> Dmac1ItrigEna0ClrDmac1ItrigInmux15

DMAC1 input trigger inmux 15 enable clear

pub const fn set_dmac1_itrig_inmux15( &mut self, val: Dmac1ItrigEna0ClrDmac1ItrigInmux15, )

DMAC1 input trigger inmux 15 enable clear

pub const fn dmac1_itrig_inmux16(&self) -> Dmac1ItrigEna0ClrDmac1ItrigInmux16

DMAC1 input trigger inmux 16 enable clear

pub const fn set_dmac1_itrig_inmux16( &mut self, val: Dmac1ItrigEna0ClrDmac1ItrigInmux16, )

DMAC1 input trigger inmux 16 enable clear

pub const fn dmac1_itrig_inmux17(&self) -> Dmac1ItrigEna0ClrDmac1ItrigInmux17

DMAC1 input trigger inmux 17 enable clear

pub const fn set_dmac1_itrig_inmux17( &mut self, val: Dmac1ItrigEna0ClrDmac1ItrigInmux17, )

DMAC1 input trigger inmux 17 enable clear

pub const fn dmac1_itrig_inmux18(&self) -> Dmac1ItrigEna0ClrDmac1ItrigInmux18

DMAC1 input trigger inmux 18 enable clear

pub const fn set_dmac1_itrig_inmux18( &mut self, val: Dmac1ItrigEna0ClrDmac1ItrigInmux18, )

DMAC1 input trigger inmux 18 enable clear

pub const fn dmac1_itrig_inmux19(&self) -> Dmac1ItrigEna0ClrDmac1ItrigInmux19

DMAC1 input trigger inmux 19 enable clear

pub const fn set_dmac1_itrig_inmux19( &mut self, val: Dmac1ItrigEna0ClrDmac1ItrigInmux19, )

DMAC1 input trigger inmux 19 enable clear

pub const fn dmac1_itrig_inmux20(&self) -> Dmac1ItrigEna0ClrDmac1ItrigInmux20

DMAC1 input trigger inmux 20 enable clear

pub const fn set_dmac1_itrig_inmux20( &mut self, val: Dmac1ItrigEna0ClrDmac1ItrigInmux20, )

DMAC1 input trigger inmux 20 enable clear

pub const fn dmac1_itrig_inmux21(&self) -> Dmac1ItrigEna0ClrDmac1ItrigInmux21

DMAC1 input trigger inmux 21 enable clear

pub const fn set_dmac1_itrig_inmux21( &mut self, val: Dmac1ItrigEna0ClrDmac1ItrigInmux21, )

DMAC1 input trigger inmux 21 enable clear

pub const fn dmac1_itrig_inmux22(&self) -> Dmac1ItrigEna0ClrDmac1ItrigInmux22

DMAC1 input trigger inmux 22 enable clear

pub const fn set_dmac1_itrig_inmux22( &mut self, val: Dmac1ItrigEna0ClrDmac1ItrigInmux22, )

DMAC1 input trigger inmux 22 enable clear

pub const fn dmac1_itrig_inmux23(&self) -> Dmac1ItrigEna0ClrDmac1ItrigInmux23

DMAC1 input trigger inmux 23 enable clear

pub const fn set_dmac1_itrig_inmux23( &mut self, val: Dmac1ItrigEna0ClrDmac1ItrigInmux23, )

DMAC1 input trigger inmux 23 enable clear

pub const fn dmac1_itrig_inmux24(&self) -> Dmac1ItrigEna0ClrDmac1ItrigInmux24

DMAC1 input trigger inmux 24 enable clear

pub const fn set_dmac1_itrig_inmux24( &mut self, val: Dmac1ItrigEna0ClrDmac1ItrigInmux24, )

DMAC1 input trigger inmux 24 enable clear

pub const fn dmac1_itrig_inmux25(&self) -> Dmac1ItrigEna0ClrDmac1ItrigInmux25

DMAC1 input trigger inmux 25 enable clear

pub const fn set_dmac1_itrig_inmux25( &mut self, val: Dmac1ItrigEna0ClrDmac1ItrigInmux25, )

DMAC1 input trigger inmux 25 enable clear

pub const fn dmac1_itrig_inmux26(&self) -> Dmac1ItrigEna0ClrDmac1ItrigInmux26

DMAC1 input trigger inmux 25 enable clear

pub const fn set_dmac1_itrig_inmux26( &mut self, val: Dmac1ItrigEna0ClrDmac1ItrigInmux26, )

DMAC1 input trigger inmux 25 enable clear

pub const fn dmac1_itrig_inmux27(&self) -> Dmac1ItrigEna0ClrDmac1ItrigInmux27

DMAC1 input trigger inmux 25 enable clear

pub const fn set_dmac1_itrig_inmux27( &mut self, val: Dmac1ItrigEna0ClrDmac1ItrigInmux27, )

DMAC1 input trigger inmux 25 enable clear

pub const fn dmac1_itrig_inmux28(&self) -> Dmac1ItrigEna0ClrDmac1ItrigInmux28

DMAC1 input trigger inmux 25 enable clear

pub const fn set_dmac1_itrig_inmux28( &mut self, val: Dmac1ItrigEna0ClrDmac1ItrigInmux28, )

DMAC1 input trigger inmux 25 enable clear

pub const fn dmac1_itrig_inmux29(&self) -> Dmac1ItrigEna0ClrDmac1ItrigInmux29

DMAC1 input trigger inmux 25 enable clear

pub const fn set_dmac1_itrig_inmux29( &mut self, val: Dmac1ItrigEna0ClrDmac1ItrigInmux29, )

DMAC1 input trigger inmux 25 enable clear

pub const fn dmac1_itrig_inmux30(&self) -> Dmac1ItrigEna0ClrDmac1ItrigInmux30

DMAC1 input trigger inmux 25 enable clear

pub const fn set_dmac1_itrig_inmux30( &mut self, val: Dmac1ItrigEna0ClrDmac1ItrigInmux30, )

DMAC1 input trigger inmux 25 enable clear

pub const fn dmac1_itrig_inmux31(&self) -> Dmac1ItrigEna0ClrDmac1ItrigInmux31

DMAC1 input trigger inmux 25 enable clear

pub const fn set_dmac1_itrig_inmux31( &mut self, val: Dmac1ItrigEna0ClrDmac1ItrigInmux31, )

DMAC1 input trigger inmux 25 enable clear

Trait Implementations

impl Clone for Dmac1ItrigEna0Clr

fn clone(&self) -> Dmac1ItrigEna0Clr

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for Dmac1ItrigEna0Clr

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Default for Dmac1ItrigEna0Clr

fn default() -> Dmac1ItrigEna0Clr

Returns the “default value” for a type.

impl PartialEq for Dmac1ItrigEna0Clr

fn eq(&self, other: &Dmac1ItrigEna0Clr) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Dmac1ItrigEna0Clr

impl Eq for Dmac1ItrigEna0Clr

impl StructuralPartialEq for Dmac1ItrigEna0Clr