#[repr(u8)]pub enum Rram {
RRAM_0 = 0,
RRAM_1 = 1,
}Variants§
RRAM_0 = 0
Register access is fully enabled. The OTFAD programming model registers can be accessed “normally”.
RRAM_1 = 1
Register access is restricted and only the CR, SR and optional MDPC registers can be accessed; others are treated as RAZ/WI.
Implementations§
Trait Implementations§
Source§impl Ord for Rram
impl Ord for Rram
Source§impl PartialOrd for Rram
impl PartialOrd for Rram
impl Copy for Rram
impl Eq for Rram
impl StructuralPartialEq for Rram
Auto Trait Implementations§
impl Freeze for Rram
impl RefUnwindSafe for Rram
impl Send for Rram
impl Sync for Rram
impl Unpin for Rram
impl UnwindSafe for Rram
Blanket Implementations§
Source§impl<T> BorrowMut<T> for Twhere
T: ?Sized,
impl<T> BorrowMut<T> for Twhere
T: ?Sized,
Source§fn borrow_mut(&mut self) -> &mut T
fn borrow_mut(&mut self) -> &mut T
Mutably borrows from an owned value. Read more