#[repr(transparent)]pub struct Dmareq1(pub u32);Expand description
SCT DMA request 1 register
Tuple Fields§
§0: u32Implementations§
Source§impl Dmareq1
impl Dmareq1
Sourcepub const fn dev_1(&self) -> u16
pub const fn dev_1(&self) -> u16
If bit n is one, event n triggers DMA request 1 (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT.
Sourcepub const fn set_dev_1(&mut self, val: u16)
pub const fn set_dev_1(&mut self, val: u16)
If bit n is one, event n triggers DMA request 1 (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT.
Sourcepub const fn drl1(&self) -> bool
pub const fn drl1(&self) -> bool
A 1 in this bit triggers DMA request 1 when it loads the Match L/Unified registers from the Reload L/Unified registers.
Sourcepub const fn set_drl1(&mut self, val: bool)
pub const fn set_drl1(&mut self, val: bool)
A 1 in this bit triggers DMA request 1 when it loads the Match L/Unified registers from the Reload L/Unified registers.
Sourcepub const fn drq1(&self) -> bool
pub const fn drq1(&self) -> bool
This read-only bit indicates the state of DMA Request 1. Note that if the related DMA channel is enabled and properly set up, it is unlikely that software will see this flag, it will be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA setup.
Sourcepub const fn set_drq1(&mut self, val: bool)
pub const fn set_drq1(&mut self, val: bool)
This read-only bit indicates the state of DMA Request 1. Note that if the related DMA channel is enabled and properly set up, it is unlikely that software will see this flag, it will be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA setup.