#[repr(transparent)]pub struct Fifocfg(pub u32);Expand description
FIFO configuration and enable register.
Tuple Fields§
§0: u32Implementations§
Source§impl Fifocfg
impl Fifocfg
Sourcepub const fn set_enabletx(&mut self, val: bool)
pub const fn set_enabletx(&mut self, val: bool)
Enable the transmit FIFO.
Sourcepub const fn set_enablerx(&mut self, val: bool)
pub const fn set_enablerx(&mut self, val: bool)
Enable the receive FIFO.
Sourcepub const fn size(&self) -> u8
pub const fn size(&self) -> u8
FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART.
Sourcepub const fn set_size(&mut self, val: u8)
pub const fn set_size(&mut self, val: u8)
FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART.
Sourcepub const fn waketx(&self) -> bool
pub const fn waketx(&self) -> bool
Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register.
Sourcepub const fn set_waketx(&mut self, val: bool)
pub const fn set_waketx(&mut self, val: bool)
Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register.
Sourcepub const fn wakerx(&self) -> bool
pub const fn wakerx(&self) -> bool
Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register.
Sourcepub const fn set_wakerx(&mut self, val: bool)
pub const fn set_wakerx(&mut self, val: bool)
Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register.
Sourcepub const fn emptytx(&self) -> bool
pub const fn emptytx(&self) -> bool
Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied.
Sourcepub const fn set_emptytx(&mut self, val: bool)
pub const fn set_emptytx(&mut self, val: bool)
Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied.
Sourcepub const fn emptyrx(&self) -> bool
pub const fn emptyrx(&self) -> bool
Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied.
Sourcepub const fn set_emptyrx(&mut self, val: bool)
pub const fn set_emptyrx(&mut self, val: bool)
Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied.