#[repr(transparent)]pub struct Ctrl(pub u32);Expand description
USB PHY General Control Register
Tuple Fields§
§0: u32Implementations§
Source§impl Ctrl
impl Ctrl
Sourcepub const fn enhostdiscondetect(&self) -> bool
pub const fn enhostdiscondetect(&self) -> bool
For host mode, enables high-speed disconnect detector
Sourcepub const fn set_enhostdiscondetect(&mut self, val: bool)
pub const fn set_enhostdiscondetect(&mut self, val: bool)
For host mode, enables high-speed disconnect detector
Sourcepub const fn hostdiscondetect_irq(&self) -> bool
pub const fn hostdiscondetect_irq(&self) -> bool
Indicates that the device has disconnected in High-Speed mode
Sourcepub const fn set_hostdiscondetect_irq(&mut self, val: bool)
pub const fn set_hostdiscondetect_irq(&mut self, val: bool)
Indicates that the device has disconnected in High-Speed mode
Sourcepub const fn endevplugindet(&self) -> CtrlEndevplugindet
pub const fn endevplugindet(&self) -> CtrlEndevplugindet
Enables non-standard resistive plugged-in detection This bit field controls connection of nominal 200kohm resistors to both the USB_DP and USB_DM pins as one method of detecting when a USB cable is attached in device mode
Sourcepub const fn set_endevplugindet(&mut self, val: CtrlEndevplugindet)
pub const fn set_endevplugindet(&mut self, val: CtrlEndevplugindet)
Enables non-standard resistive plugged-in detection This bit field controls connection of nominal 200kohm resistors to both the USB_DP and USB_DM pins as one method of detecting when a USB cable is attached in device mode
Sourcepub const fn devplugin_irq(&self) -> bool
pub const fn devplugin_irq(&self) -> bool
Indicates that the device is connected
Sourcepub const fn set_devplugin_irq(&mut self, val: bool)
pub const fn set_devplugin_irq(&mut self, val: bool)
Indicates that the device is connected
Sourcepub const fn enutmilevel2(&self) -> bool
pub const fn enutmilevel2(&self) -> bool
Enables UTMI+ Level 2 operation for the USB HS PHY
Sourcepub const fn set_enutmilevel2(&mut self, val: bool)
pub const fn set_enutmilevel2(&mut self, val: bool)
Enables UTMI+ Level 2 operation for the USB HS PHY
Sourcepub const fn enutmilevel3(&self) -> bool
pub const fn enutmilevel3(&self) -> bool
Enables UTMI+ Level 3 operation for the USB HS PHY
Sourcepub const fn set_enutmilevel3(&mut self, val: bool)
pub const fn set_enutmilevel3(&mut self, val: bool)
Enables UTMI+ Level 3 operation for the USB HS PHY
Sourcepub const fn autoresume_en(&self) -> bool
pub const fn autoresume_en(&self) -> bool
Enable the auto resume feature, when set, HW will use 32KHz clock to send Resume to respond to the device remote wakeup(for host mode only)
Sourcepub const fn set_autoresume_en(&mut self, val: bool)
pub const fn set_autoresume_en(&mut self, val: bool)
Enable the auto resume feature, when set, HW will use 32KHz clock to send Resume to respond to the device remote wakeup(for host mode only)
Sourcepub const fn enautoclr_clkgate(&self) -> bool
pub const fn enautoclr_clkgate(&self) -> bool
Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended
Sourcepub const fn set_enautoclr_clkgate(&mut self, val: bool)
pub const fn set_enautoclr_clkgate(&mut self, val: bool)
Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended
Sourcepub const fn enautoclr_phy_pwd(&self) -> bool
pub const fn enautoclr_phy_pwd(&self) -> bool
Enables the feature to auto-clear the PWD register bits in PWD if there is wakeup event while USB is suspended
Sourcepub const fn set_enautoclr_phy_pwd(&mut self, val: bool)
pub const fn set_enautoclr_phy_pwd(&mut self, val: bool)
Enables the feature to auto-clear the PWD register bits in PWD if there is wakeup event while USB is suspended
Sourcepub const fn fsdll_rst_en(&self) -> bool
pub const fn fsdll_rst_en(&self) -> bool
Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet.
Sourcepub const fn set_fsdll_rst_en(&mut self, val: bool)
pub const fn set_fsdll_rst_en(&mut self, val: bool)
Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet.
Sourcepub const fn host_force_ls_se0(&self) -> bool
pub const fn host_force_ls_se0(&self) -> bool
Forces the next FS packet that is transmitted to have a EOP with low-speed timing
Sourcepub const fn set_host_force_ls_se0(&mut self, val: bool)
pub const fn set_host_force_ls_se0(&mut self, val: bool)
Forces the next FS packet that is transmitted to have a EOP with low-speed timing
Sourcepub const fn utmi_suspendm(&self) -> bool
pub const fn utmi_suspendm(&self) -> bool
Used by the PHY to indicate a powered-down state
Sourcepub const fn set_utmi_suspendm(&mut self, val: bool)
pub const fn set_utmi_suspendm(&mut self, val: bool)
Used by the PHY to indicate a powered-down state
Sourcepub const fn set_clkgate(&mut self, val: bool)
pub const fn set_clkgate(&mut self, val: bool)
Gate UTMI Clocks
Sourcepub const fn sftrst(&self) -> bool
pub const fn sftrst(&self) -> bool
Writing a 1 to this bit will soft-reset the PWD, TX, RX, and CTRL registers
Sourcepub const fn set_sftrst(&mut self, val: bool)
pub const fn set_sftrst(&mut self, val: bool)
Writing a 1 to this bit will soft-reset the PWD, TX, RX, and CTRL registers