#[repr(transparent)]pub struct Debug0Tog(pub u32);Expand description
USB PHY Debug Register 0
Tuple Fields§
§0: u32Implementations§
Source§impl Debug0Tog
impl Debug0Tog
Sourcepub const fn debug_interface_hold(&self) -> bool
pub const fn debug_interface_hold(&self) -> bool
Use holding registers to assist in timing for external UTMI interface.
Sourcepub const fn set_debug_interface_hold(&mut self, val: bool)
pub const fn set_debug_interface_hold(&mut self, val: bool)
Use holding registers to assist in timing for external UTMI interface.
Sourcepub const fn hstpulldown(&self) -> u8
pub const fn hstpulldown(&self) -> u8
This bit field selects whether to connect pulldown resistors on the USB_DP/USB_DM pins if the corresponding pulldown overdrive mode is enabled through DEBUG[5:4} Set bit 3 to value 1’b1 to connect the 15ohm pulldown on USB_DP line
Sourcepub const fn set_hstpulldown(&mut self, val: u8)
pub const fn set_hstpulldown(&mut self, val: u8)
This bit field selects whether to connect pulldown resistors on the USB_DP/USB_DM pins if the corresponding pulldown overdrive mode is enabled through DEBUG[5:4} Set bit 3 to value 1’b1 to connect the 15ohm pulldown on USB_DP line
Sourcepub const fn enhstpulldown(&self) -> u8
pub const fn enhstpulldown(&self) -> u8
This bit field selects host pulldown overdrive mode
Sourcepub const fn set_enhstpulldown(&mut self, val: u8)
pub const fn set_enhstpulldown(&mut self, val: u8)
This bit field selects host pulldown overdrive mode
Sourcepub const fn tx2rxcount(&self) -> u8
pub const fn tx2rxcount(&self) -> u8
Delay in between the end of transmit to the beginning of receive
Sourcepub const fn set_tx2rxcount(&mut self, val: u8)
pub const fn set_tx2rxcount(&mut self, val: u8)
Delay in between the end of transmit to the beginning of receive
Sourcepub const fn entx2rxcount(&self) -> bool
pub const fn entx2rxcount(&self) -> bool
Set this bit to allow a countdown to transition in between TX and RX.
Sourcepub const fn set_entx2rxcount(&mut self, val: bool)
pub const fn set_entx2rxcount(&mut self, val: bool)
Set this bit to allow a countdown to transition in between TX and RX.
Sourcepub const fn squelchresetcount(&self) -> u8
pub const fn squelchresetcount(&self) -> u8
Delay in between the detection of squelch to the reset of high-speed RX.
Sourcepub const fn set_squelchresetcount(&mut self, val: u8)
pub const fn set_squelchresetcount(&mut self, val: u8)
Delay in between the detection of squelch to the reset of high-speed RX.
Sourcepub const fn ensquelchreset(&self) -> bool
pub const fn ensquelchreset(&self) -> bool
Set bit to allow squelch to reset high-speed receive.
Sourcepub const fn set_ensquelchreset(&mut self, val: bool)
pub const fn set_ensquelchreset(&mut self, val: bool)
Set bit to allow squelch to reset high-speed receive.
Sourcepub const fn squelchresetlength(&self) -> u8
pub const fn squelchresetlength(&self) -> u8
Duration of RESET in terms of the number of 480-MHz cycles.
Sourcepub const fn set_squelchresetlength(&mut self, val: u8)
pub const fn set_squelchresetlength(&mut self, val: u8)
Duration of RESET in terms of the number of 480-MHz cycles.
Sourcepub const fn host_resume_debug(&self) -> bool
pub const fn host_resume_debug(&self) -> bool
Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1.
Sourcepub const fn set_host_resume_debug(&mut self, val: bool)
pub const fn set_host_resume_debug(&mut self, val: bool)
Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1.
Sourcepub const fn set_clkgate(&mut self, val: bool)
pub const fn set_clkgate(&mut self, val: bool)
Gate Test Clocks