rp-pac

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git

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rp2040

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Module rp_pac::pll::regs

source ·

Structs§

  • Control and Status GENERAL CONSTRAINTS: Reference clock frequency min=5MHz, max=800MHz Feedback divider min=16, max=320 VCO frequency min=750MHz, max=1600MHz
  • Feedback divisor (note: this PLL does not support fractional division)
  • Controls the PLL post dividers for the primary output (note: this PLL does not have a secondary output) the primary output is driven from VCO divided by postdiv1*postdiv2
  • Controls the PLL power modes.