#[repr(transparent)]pub struct Cs(pub u32);
Expand description
Control and Status GENERAL CONSTRAINTS: Reference clock frequency min=5MHz, max=800MHz Feedback divider min=16, max=320 VCO frequency min=750MHz, max=1600MHz
Tuple Fields§
§0: u32
Implementations§
Source§impl Cs
impl Cs
Sourcepub const fn refdiv(&self) -> u8
pub const fn refdiv(&self) -> u8
Divides the PLL input reference clock. Behaviour is undefined for div=0. PLL output will be unpredictable during refdiv changes, wait for lock=1 before using it.
Sourcepub fn set_refdiv(&mut self, val: u8)
pub fn set_refdiv(&mut self, val: u8)
Divides the PLL input reference clock. Behaviour is undefined for div=0. PLL output will be unpredictable during refdiv changes, wait for lock=1 before using it.
Sourcepub const fn bypass(&self) -> bool
pub const fn bypass(&self) -> bool
Passes the reference clock to the output instead of the divided VCO. The VCO continues to run so the user can switch between the reference clock and the divided VCO but the output will glitch when doing so.
Sourcepub fn set_bypass(&mut self, val: bool)
pub fn set_bypass(&mut self, val: bool)
Passes the reference clock to the output instead of the divided VCO. The VCO continues to run so the user can switch between the reference clock and the divided VCO but the output will glitch when doing so.