#[repr(transparent)]pub struct FifoSt(pub u32);
Expand description
Status register for inter-core FIFOs (mailboxes). There is one FIFO in the core 0 -> core 1 direction, and one core 1 -> core 0. Both are 32 bits wide and 8 words deep. Core 0 can see the read side of the 1->0 FIFO (RX), and the write side of 0->1 FIFO (TX). Core 1 can see the read side of the 0->1 FIFO (RX), and the write side of 1->0 FIFO (TX). The SIO IRQ for each core is the logical OR of the VLD, WOF and ROE fields of its FIFO_ST register.
Tuple Fields§
§0: u32
Implementations§
Source§impl FifoSt
impl FifoSt
Sourcepub const fn vld(&self) -> bool
pub const fn vld(&self) -> bool
Value is 1 if this core’s RX FIFO is not empty (i.e. if FIFO_RD is valid)
Sourcepub fn set_vld(&mut self, val: bool)
pub fn set_vld(&mut self, val: bool)
Value is 1 if this core’s RX FIFO is not empty (i.e. if FIFO_RD is valid)
Sourcepub const fn rdy(&self) -> bool
pub const fn rdy(&self) -> bool
Value is 1 if this core’s TX FIFO is not full (i.e. if FIFO_WR is ready for more data)
Sourcepub fn set_rdy(&mut self, val: bool)
pub fn set_rdy(&mut self, val: bool)
Value is 1 if this core’s TX FIFO is not full (i.e. if FIFO_WR is ready for more data)
Sourcepub const fn wof(&self) -> bool
pub const fn wof(&self) -> bool
Sticky flag indicating the TX FIFO was written when full. This write was ignored by the FIFO.
Sourcepub fn set_wof(&mut self, val: bool)
pub fn set_wof(&mut self, val: bool)
Sticky flag indicating the TX FIFO was written when full. This write was ignored by the FIFO.