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Struct rp_pac::sio::regs::Interp1ctrlLane0

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#[repr(transparent)]
pub struct Interp1ctrlLane0(pub u32);
Expand description

Control register for lane 0

Tuple Fields§

§0: u32

Implementations§

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impl Interp1ctrlLane0

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pub const fn shift(&self) -> u8

Logical right-shift applied to accumulator before masking

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pub fn set_shift(&mut self, val: u8)

Logical right-shift applied to accumulator before masking

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pub const fn mask_lsb(&self) -> u8

The least-significant bit allowed to pass by the mask (inclusive)

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pub fn set_mask_lsb(&mut self, val: u8)

The least-significant bit allowed to pass by the mask (inclusive)

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pub const fn mask_msb(&self) -> u8

The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out

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pub fn set_mask_msb(&mut self, val: u8)

The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out

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pub const fn signed(&self) -> bool

If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor.

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pub fn set_signed(&mut self, val: bool)

If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor.

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pub const fn cross_input(&self) -> bool

If 1, feed the opposite lane’s accumulator into this lane’s shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)

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pub fn set_cross_input(&mut self, val: bool)

If 1, feed the opposite lane’s accumulator into this lane’s shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)

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pub const fn cross_result(&self) -> bool

If 1, feed the opposite lane’s result into this lane’s accumulator on POP.

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pub fn set_cross_result(&mut self, val: bool)

If 1, feed the opposite lane’s result into this lane’s accumulator on POP.

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pub const fn add_raw(&self) -> bool

If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result.

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pub fn set_add_raw(&mut self, val: bool)

If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result.

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pub const fn force_msb(&self) -> u8

ORed into bits 29:28 of the lane result presented to the processor on the bus. No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence of pointers into flash or SRAM.

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pub fn set_force_msb(&mut self, val: u8)

ORed into bits 29:28 of the lane result presented to the processor on the bus. No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence of pointers into flash or SRAM.

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pub const fn clamp(&self) -> bool

Only present on INTERP1 on each core. If CLAMP mode is enabled: - LANE0 result is shifted and masked ACCUM0, clamped by a lower bound of BASE0 and an upper bound of BASE1. - Signedness of these comparisons is determined by LANE0_CTRL_SIGNED

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pub fn set_clamp(&mut self, val: bool)

Only present on INTERP1 on each core. If CLAMP mode is enabled: - LANE0 result is shifted and masked ACCUM0, clamped by a lower bound of BASE0 and an upper bound of BASE1. - Signedness of these comparisons is determined by LANE0_CTRL_SIGNED

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pub const fn overf0(&self) -> bool

Indicates if any masked-off MSBs in ACCUM0 are set.

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pub fn set_overf0(&mut self, val: bool)

Indicates if any masked-off MSBs in ACCUM0 are set.

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pub const fn overf1(&self) -> bool

Indicates if any masked-off MSBs in ACCUM1 are set.

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pub fn set_overf1(&mut self, val: bool)

Indicates if any masked-off MSBs in ACCUM1 are set.

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pub const fn overf(&self) -> bool

Set if either OVERF0 or OVERF1 is set.

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pub fn set_overf(&mut self, val: bool)

Set if either OVERF0 or OVERF1 is set.

Trait Implementations§

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impl Clone for Interp1ctrlLane0

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fn clone(&self) -> Interp1ctrlLane0

Returns a copy of the value. Read more
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fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source. Read more
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impl Default for Interp1ctrlLane0

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fn default() -> Interp1ctrlLane0

Returns the “default value” for a type. Read more
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impl PartialEq for Interp1ctrlLane0

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fn eq(&self, other: &Interp1ctrlLane0) -> bool

Tests for self and other values to be equal, and is used by ==.
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fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.
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impl Copy for Interp1ctrlLane0

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impl Eq for Interp1ctrlLane0

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impl StructuralPartialEq for Interp1ctrlLane0

Auto Trait Implementations§

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impl<T> Any for T
where T: 'static + ?Sized,

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fn type_id(&self) -> TypeId

Gets the TypeId of self. Read more
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impl<T> Borrow<T> for T
where T: ?Sized,

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fn borrow(&self) -> &T

Immutably borrows from an owned value. Read more
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impl<T> BorrowMut<T> for T
where T: ?Sized,

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fn borrow_mut(&mut self) -> &mut T

Mutably borrows from an owned value. Read more
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impl<T> CloneToUninit for T
where T: Clone,

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unsafe fn clone_to_uninit(&self, dst: *mut T)

🔬This is a nightly-only experimental API. (clone_to_uninit)
Performs copy-assignment from self to dst. Read more
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impl<T> From<T> for T

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fn from(t: T) -> T

Returns the argument unchanged.

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impl<T, U> Into<U> for T
where U: From<T>,

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fn into(self) -> U

Calls U::from(self).

That is, this conversion is whatever the implementation of From<T> for U chooses to do.

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impl<T, U> TryFrom<U> for T
where U: Into<T>,

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type Error = Infallible

The type returned in the event of a conversion error.
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fn try_from(value: U) -> Result<T, <T as TryFrom<U>>::Error>

Performs the conversion.
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impl<T, U> TryInto<U> for T
where U: TryFrom<T>,

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type Error = <U as TryFrom<T>>::Error

The type returned in the event of a conversion error.
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fn try_into(self) -> Result<U, <U as TryFrom<T>>::Error>

Performs the conversion.