Struct rp_pac::uart::regs::UartlcrH

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#[repr(transparent)]
pub struct UartlcrH(pub u32);

Expand description

Line Control Register, UARTLCR_H

Tuple Fields§

§0: u32

Implementations§

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impl UartlcrH

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pub const fn brk(&self) -> bool

Send break. If this bit is set to 1, a low-level is continually output on the UARTTXD output, after completing transmission of the current character. For the proper execution of the break command, the software must set this bit for at least two complete frames. For normal use, this bit must be cleared to 0.

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pub fn set_brk(&mut self, val: bool)

Send break. If this bit is set to 1, a low-level is continually output on the UARTTXD output, after completing transmission of the current character. For the proper execution of the break command, the software must set this bit for at least two complete frames. For normal use, this bit must be cleared to 0.

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pub const fn pen(&self) -> bool

Parity enable: 0 = parity is disabled and no parity bit added to the data frame 1 = parity checking and generation is enabled.

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pub fn set_pen(&mut self, val: bool)

Parity enable: 0 = parity is disabled and no parity bit added to the data frame 1 = parity checking and generation is enabled.

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pub const fn eps(&self) -> bool

Even parity select. Controls the type of parity the UART uses during transmission and reception: 0 = odd parity. The UART generates or checks for an odd number of 1s in the data and parity bits. 1 = even parity. The UART generates or checks for an even number of 1s in the data and parity bits. This bit has no effect when the PEN bit disables parity checking and generation.

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pub fn set_eps(&mut self, val: bool)

Even parity select. Controls the type of parity the UART uses during transmission and reception: 0 = odd parity. The UART generates or checks for an odd number of 1s in the data and parity bits. 1 = even parity. The UART generates or checks for an even number of 1s in the data and parity bits. This bit has no effect when the PEN bit disables parity checking and generation.

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pub const fn stp2(&self) -> bool

Two stop bits select. If this bit is set to 1, two stop bits are transmitted at the end of the frame. The receive logic does not check for two stop bits being received.

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pub fn set_stp2(&mut self, val: bool)

Two stop bits select. If this bit is set to 1, two stop bits are transmitted at the end of the frame. The receive logic does not check for two stop bits being received.

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pub const fn fen(&self) -> bool

Enable FIFOs: 0 = FIFOs are disabled (character mode) that is, the FIFOs become 1-byte-deep holding registers 1 = transmit and receive FIFO buffers are enabled (FIFO mode).

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pub fn set_fen(&mut self, val: bool)

Enable FIFOs: 0 = FIFOs are disabled (character mode) that is, the FIFOs become 1-byte-deep holding registers 1 = transmit and receive FIFO buffers are enabled (FIFO mode).

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pub const fn wlen(&self) -> u8

Word length. These bits indicate the number of data bits transmitted or received in a frame as follows: b11 = 8 bits b10 = 7 bits b01 = 6 bits b00 = 5 bits.

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pub fn set_wlen(&mut self, val: u8)

Word length. These bits indicate the number of data bits transmitted or received in a frame as follows: b11 = 8 bits b10 = 7 bits b01 = 6 bits b00 = 5 bits.

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pub const fn sps(&self) -> bool

Stick parity select. 0 = stick parity is disabled 1 = either: * if the EPS bit is 0 then the parity bit is transmitted and checked as a 1 * if the EPS bit is 1 then the parity bit is transmitted and checked as a 0. This bit has no effect when the PEN bit disables parity checking and generation.

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pub fn set_sps(&mut self, val: bool)

Stick parity select. 0 = stick parity is disabled 1 = either: * if the EPS bit is 0 then the parity bit is transmitted and checked as a 1 * if the EPS bit is 1 then the parity bit is transmitted and checked as a 0. This bit has no effect when the PEN bit disables parity checking and generation.