Struct rp_pac::dma::Dma

pub struct Dma { /* private fields */ }

DMA with separate read and write masters

Implementations

impl Dma

pub const unsafe fn from_ptr(ptr: *mut ()) -> Self

pub const fn as_ptr(&self) -> *mut ()

pub const fn ch(self, n: usize) -> Channel

pub const fn intr(self, n: usize) -> Reg<u32, RW>

Interrupt Status (raw)

pub const fn inte(self, n: usize) -> Reg<u32, RW>

Interrupt Enables for IRQ 0

pub const fn intf(self, n: usize) -> Reg<u32, RW>

Force Interrupts

pub const fn ints(self, n: usize) -> Reg<u32, RW>

Interrupt Status for IRQ 0

pub const fn timer(self, n: usize) -> Reg<Timer, RW>

Pacing (X/Y) fractional timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.

pub const fn multi_chan_trigger(self) -> Reg<MultiChanTrigger, RW>

Trigger one or more channels simultaneously

pub const fn sniff_ctrl(self) -> Reg<SniffCtrl, RW>

Sniffer Control

pub const fn sniff_data(self) -> Reg<u32, RW>

Data accumulator for sniff hardware

pub const fn fifo_levels(self) -> Reg<FifoLevels, RW>

Debug RAF, WAF, TDF levels

pub const fn chan_abort(self) -> Reg<ChanAbort, RW>

Abort an in-progress transfer sequence on one or more channels

pub const fn n_channels(self) -> Reg<Nchannels, RW>

The number of channels this DMA instance is equipped with. This DMA supports up to 16 hardware channels, but can be configured with as few as one, to minimise silicon area.

pub const fn seccfg_ch(self, n: usize) -> Reg<SeccfgCh, RW>

Security configuration for channel 0. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context.

pub const fn seccfg_irq(self, n: usize) -> Reg<SeccfgIrq, RW>

Security configuration for IRQ 0. Control whether the IRQ permits configuration by Non-secure/Unprivileged contexts, and whether it can observe Secure/Privileged channel interrupt flags.

pub const fn seccfg_misc(self) -> Reg<SeccfgMisc, RW>

Miscellaneous security configuration

pub const fn mpu_ctrl(self) -> Reg<MpuCtrl, RW>

Control register for DMA MPU. Accessible only from a Privileged context.

pub const fn mpu_bar(self, n: usize) -> Reg<u32, RW>

Base address register for MPU region 0. Writable only from a Secure, Privileged context.

pub const fn mpu_lar(self, n: usize) -> Reg<u32, RW>

Limit address register for MPU region 0. Writable only from a Secure, Privileged context, with the exception of the P bit.

Trait Implementations

impl Clone for Dma

fn clone(&self) -> Dma

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl PartialEq for Dma

fn eq(&self, other: &Dma) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Dma

impl Eq for Dma

impl Send for Dma

impl StructuralPartialEq for Dma

impl Sync for Dma