Struct Pll1cfgr
#[repr(transparent)]pub struct Pll1cfgr(pub u32);Expand description
RCC PLL1 configuration register
Tuple Fields§
§0: u32Implementations§
§impl Pll1cfgr
impl Pll1cfgr
pub const fn pllsrc(&self) -> Pllsrc
pub const fn pllsrc(&self) -> Pllsrc
PLL1 entry clock source Set and cleared by software to select PLL1 clock source. These bits can be written only when the PLL1 is disabled. In order to save power, when no PLL1 is used, the value of PLL1SRC must be 0.
pub fn set_pllsrc(&mut self, val: Pllsrc)
pub fn set_pllsrc(&mut self, val: Pllsrc)
PLL1 entry clock source Set and cleared by software to select PLL1 clock source. These bits can be written only when the PLL1 is disabled. In order to save power, when no PLL1 is used, the value of PLL1SRC must be 0.
pub const fn pllrge(&self) -> Pllrge
pub const fn pllrge(&self) -> Pllrge
PLL1 input frequency range Set and reset by software to select the proper reference frequency range used for PLL1. This bit must be written before enabling the PLL1. 00-01-10: PLL1 input (ref1_ck) clock range frequency between 4 and 8 MHz
pub fn set_pllrge(&mut self, val: Pllrge)
pub fn set_pllrge(&mut self, val: Pllrge)
PLL1 input frequency range Set and reset by software to select the proper reference frequency range used for PLL1. This bit must be written before enabling the PLL1. 00-01-10: PLL1 input (ref1_ck) clock range frequency between 4 and 8 MHz
pub const fn pllfracen(&self) -> bool
pub const fn pllfracen(&self) -> bool
PLL1 fractional latch enable Set and reset by software to latch the content of PLL1FRACN into the ΣΠmodulator. In order to latch the PLL1FRACN value into the ΣΠmodulator, PLL1FRACEN must be set to 0, then set to 1: the transition 0 to 1 transfers the content of PLL1FRACN into the modulator (see for details).
pub fn set_pllfracen(&mut self, val: bool)
pub fn set_pllfracen(&mut self, val: bool)
PLL1 fractional latch enable Set and reset by software to latch the content of PLL1FRACN into the ΣΠmodulator. In order to latch the PLL1FRACN value into the ΣΠmodulator, PLL1FRACEN must be set to 0, then set to 1: the transition 0 to 1 transfers the content of PLL1FRACN into the modulator (see for details).
pub const fn pllm(&self) -> Pllm
pub const fn pllm(&self) -> Pllm
Prescaler for PLL1 Set and cleared by software to configure the prescaler of the PLL1. The VCO1 input frequency is PLL1 input clock frequency/PLL1M. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). …
pub fn set_pllm(&mut self, val: Pllm)
pub fn set_pllm(&mut self, val: Pllm)
Prescaler for PLL1 Set and cleared by software to configure the prescaler of the PLL1. The VCO1 input frequency is PLL1 input clock frequency/PLL1M. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). …
pub const fn pllmboost(&self) -> Pllmboost
pub const fn pllmboost(&self) -> Pllmboost
Prescaler for EPOD booster input clock Set and cleared by software to configure the prescaler of the PLL1, used for the EPOD booster. The EPOD booster input frequency is PLL1 input clock frequency/PLL1MBOOST. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0) and EPOD Boost mode is disabled (see ). others: reserved
pub fn set_pllmboost(&mut self, val: Pllmboost)
pub fn set_pllmboost(&mut self, val: Pllmboost)
Prescaler for EPOD booster input clock Set and cleared by software to configure the prescaler of the PLL1, used for the EPOD booster. The EPOD booster input frequency is PLL1 input clock frequency/PLL1MBOOST. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0) and EPOD Boost mode is disabled (see ). others: reserved
pub const fn pllpen(&self) -> bool
pub const fn pllpen(&self) -> bool
PLL1 DIVP divider output enable Set and reset by software to enable the pll1_p_ck output of the PLL1. To save power, PLL1PEN and PLL1P bits must be set to 0 when the pll1_p_ck is not used. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).
pub fn set_pllpen(&mut self, val: bool)
pub fn set_pllpen(&mut self, val: bool)
PLL1 DIVP divider output enable Set and reset by software to enable the pll1_p_ck output of the PLL1. To save power, PLL1PEN and PLL1P bits must be set to 0 when the pll1_p_ck is not used. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).
pub const fn pllqen(&self) -> bool
pub const fn pllqen(&self) -> bool
PLL1 DIVQ divider output enable Set and reset by software to enable the pll1_q_ck output of the PLL1. To save power, PLL1QEN and PLL1Q bits must be set to 0 when the pll1_q_ck is not used. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).
pub fn set_pllqen(&mut self, val: bool)
pub fn set_pllqen(&mut self, val: bool)
PLL1 DIVQ divider output enable Set and reset by software to enable the pll1_q_ck output of the PLL1. To save power, PLL1QEN and PLL1Q bits must be set to 0 when the pll1_q_ck is not used. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).
pub const fn pllren(&self) -> bool
pub const fn pllren(&self) -> bool
PLL1 DIVR divider output enable Set and reset by software to enable the pll1_r_ck output of the PLL1. To save power, PLL1RENPLL2REN and PLL1R bits must be set to 0 when the pll1_r_ck is not used. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).
pub fn set_pllren(&mut self, val: bool)
pub fn set_pllren(&mut self, val: bool)
PLL1 DIVR divider output enable Set and reset by software to enable the pll1_r_ck output of the PLL1. To save power, PLL1RENPLL2REN and PLL1R bits must be set to 0 when the pll1_r_ck is not used. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).