Struct Pll2cfgr
#[repr(transparent)]pub struct Pll2cfgr(pub u32);Expand description
RCC PLL2 configuration register
Tuple Fields§
§0: u32Implementations§
§impl Pll2cfgr
impl Pll2cfgr
pub const fn pllsrc(&self) -> Pllsrc
pub const fn pllsrc(&self) -> Pllsrc
PLL2 entry clock source Set and cleared by software to select PLL2 clock source. These bits can be written only when the PLL2 is disabled. In order to save power, when no PLL2 is used, the value of PLL2SRC must be 0.
pub fn set_pllsrc(&mut self, val: Pllsrc)
pub fn set_pllsrc(&mut self, val: Pllsrc)
PLL2 entry clock source Set and cleared by software to select PLL2 clock source. These bits can be written only when the PLL2 is disabled. In order to save power, when no PLL2 is used, the value of PLL2SRC must be 0.
pub const fn pllrge(&self) -> Pllrge
pub const fn pllrge(&self) -> Pllrge
PLL2 input frequency range Set and reset by software to select the proper reference frequency range used for PLL2. This bit must be written before enabling the PLL2. 00-01-10: PLL2 input (ref2_ck) clock range frequency between 4 and 8 MHz
pub fn set_pllrge(&mut self, val: Pllrge)
pub fn set_pllrge(&mut self, val: Pllrge)
PLL2 input frequency range Set and reset by software to select the proper reference frequency range used for PLL2. This bit must be written before enabling the PLL2. 00-01-10: PLL2 input (ref2_ck) clock range frequency between 4 and 8 MHz
pub const fn pllfracen(&self) -> bool
pub const fn pllfracen(&self) -> bool
PLL2 fractional latch enable Set and reset by software to latch the content of PLL2FRACN into the ΣΠmodulator. In order to latch the PLL2FRACN value into the ΣΠmodulator, PLL2FRACEN must be set to 0, then set to 1: the transition 0 to 1 transfers the content of PLL2FRACN into the modulator (see for details).
pub fn set_pllfracen(&mut self, val: bool)
pub fn set_pllfracen(&mut self, val: bool)
PLL2 fractional latch enable Set and reset by software to latch the content of PLL2FRACN into the ΣΠmodulator. In order to latch the PLL2FRACN value into the ΣΠmodulator, PLL2FRACEN must be set to 0, then set to 1: the transition 0 to 1 transfers the content of PLL2FRACN into the modulator (see for details).
pub const fn pllm(&self) -> Pllm
pub const fn pllm(&self) -> Pllm
Prescaler for PLL2 Set and cleared by software to configure the prescaler of the PLL2. The VCO2 input frequency is PLL2 input clock frequency/PLL2M. This bit can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0). …
pub fn set_pllm(&mut self, val: Pllm)
pub fn set_pllm(&mut self, val: Pllm)
Prescaler for PLL2 Set and cleared by software to configure the prescaler of the PLL2. The VCO2 input frequency is PLL2 input clock frequency/PLL2M. This bit can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0). …
pub const fn pllpen(&self) -> bool
pub const fn pllpen(&self) -> bool
PLL2 DIVP divider output enable Set and reset by software to enable the pll2_p_ck output of the PLL2. To save power, PLL2PEN and PLL2P bits must be set to 0 when the pll2_p_ck is not used. This bit can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0).
pub fn set_pllpen(&mut self, val: bool)
pub fn set_pllpen(&mut self, val: bool)
PLL2 DIVP divider output enable Set and reset by software to enable the pll2_p_ck output of the PLL2. To save power, PLL2PEN and PLL2P bits must be set to 0 when the pll2_p_ck is not used. This bit can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0).
pub const fn pllqen(&self) -> bool
pub const fn pllqen(&self) -> bool
PLL2 DIVQ divider output enable Set and reset by software to enable the pll2_q_ck output of the PLL2. To save power, PLL2QEN and PLL2Q bits must be set to 0 when the pll2_q_ck is not used. This bit can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0.
pub fn set_pllqen(&mut self, val: bool)
pub fn set_pllqen(&mut self, val: bool)
PLL2 DIVQ divider output enable Set and reset by software to enable the pll2_q_ck output of the PLL2. To save power, PLL2QEN and PLL2Q bits must be set to 0 when the pll2_q_ck is not used. This bit can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0.
pub const fn pllren(&self) -> bool
pub const fn pllren(&self) -> bool
PLL2 DIVR divider output enable Set and reset by software to enable the pll2_r_ck output of the PLL2. To save power, PLL2REN and PLL2R bits must be set to 0 when the pll2_r_ck is not used. This bit can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0).
pub fn set_pllren(&mut self, val: bool)
pub fn set_pllren(&mut self, val: bool)
PLL2 DIVR divider output enable Set and reset by software to enable the pll2_r_ck output of the PLL2. To save power, PLL2REN and PLL2R bits must be set to 0 when the pll2_r_ck is not used. This bit can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0).