Struct Syscon 

pub struct Syscon { /* private fields */ }

SYSCON

Implementations

impl Syscon

pub const unsafe fn from_ptr(ptr: *mut ()) -> Self

pub const fn as_ptr(&self) -> *mut ()

pub const fn memoryremap(self) -> Reg<Memoryremap, RW>

Memory Remap control register

pub const fn ahbmatprio(self) -> Reg<Ahbmatprio, RW>

AHB Matrix priority control register Priority values are 3 = highest, 0 = lowest

pub const fn cpu0stckcal(self) -> Reg<Cpu0stckcal, RW>

System tick calibration for secure part of CPU0

pub const fn cpu0nstckcal(self) -> Reg<Cpu0nstckcal, RW>

System tick calibration for non-secure part of CPU0

pub const fn nmisrc(self) -> Reg<Nmisrc, RW>

NMI Source Select

pub const fn presetctrl0(self) -> Reg<Presetctrl0, RW>

Peripheral reset control 0

pub const fn presetctrl1(self) -> Reg<Presetctrl1, RW>

Peripheral reset control 1

pub const fn presetctrl2(self) -> Reg<Presetctrl2, RW>

Peripheral reset control 2

pub const fn presetctrlset(self, n: usize) -> Reg<Presetctrlset, RW>

Peripheral reset control set register

pub const fn presetctrlclr(self, n: usize) -> Reg<Presetctrlclr, RW>

Peripheral reset control clear register

pub const fn swr_reset(self) -> Reg<SwrReset, W>

generate a software_reset

pub const fn ahbclkctrl0(self) -> Reg<Ahbclkctrl0, RW>

AHB Clock control 0

pub const fn ahbclkctrl1(self) -> Reg<Ahbclkctrl1, RW>

AHB Clock control 1

pub const fn ahbclkctrl2(self) -> Reg<Ahbclkctrl2, RW>

AHB Clock control 2

pub const fn ahbclkctrlset(self, n: usize) -> Reg<Ahbclkctrlset, RW>

Peripheral reset control register

pub const fn ahbclkctrlclr(self, n: usize) -> Reg<Ahbclkctrlclr, RW>

Peripheral reset control register

pub const fn systickclksel0(self) -> Reg<Systickclksel0, RW>

System Tick Timer for CPU0 source select

pub const fn systickclkselx0(self) -> Reg<Systickclkselx0, RW>

Peripheral reset control register

pub const fn traceclksel(self) -> Reg<Traceclksel, RW>

Trace clock source select

pub const fn ctimerclksel0(self) -> Reg<Ctimerclksel0, RW>

CTimer 0 clock source select

pub const fn ctimerclkselx0(self) -> Reg<Ctimerclkselx0, RW>

Peripheral reset control register

pub const fn ctimerclksel1(self) -> Reg<Ctimerclksel1, RW>

CTimer 1 clock source select

pub const fn ctimerclkselx1(self) -> Reg<Ctimerclkselx1, RW>

Peripheral reset control register

pub const fn ctimerclksel2(self) -> Reg<Ctimerclksel2, RW>

CTimer 2 clock source select

pub const fn ctimerclkselx2(self) -> Reg<Ctimerclkselx2, RW>

Peripheral reset control register

pub const fn ctimerclksel3(self) -> Reg<Ctimerclksel3, RW>

CTimer 3 clock source select

pub const fn ctimerclkselx3(self) -> Reg<Ctimerclkselx3, RW>

Peripheral reset control register

pub const fn ctimerclksel4(self) -> Reg<Ctimerclksel4, RW>

CTimer 4 clock source select

pub const fn ctimerclkselx4(self) -> Reg<Ctimerclkselx4, RW>

Peripheral reset control register

pub const fn mainclksela(self) -> Reg<Mainclksela, RW>

Main clock A source select

pub const fn mainclkselb(self) -> Reg<Mainclkselb, RW>

Main clock source select

pub const fn clkoutsel(self) -> Reg<Clkoutsel, RW>

CLKOUT clock source select

pub const fn pll0clksel(self) -> Reg<Pll0clksel, RW>

PLL0 clock source select

pub const fn pll1clksel(self) -> Reg<Pll1clksel, RW>

PLL1 clock source select

pub const fn canclksel(self) -> Reg<Canclksel, RW>

CAN clock source select

pub const fn adcclksel(self) -> Reg<Adcclksel, RW>

ADC clock source select

pub const fn usb0clksel(self) -> Reg<Usb0clksel, RW>

FS USB clock source select

pub const fn clk32kclksel(self) -> Reg<Clk32kclksel, RW>

clock low speed source select for HS USB.

pub const fn fcckkselx(self, n: usize) -> Reg<Fcclkselx, RW>

Peripheral reset control register

pub const fn fcclksel(self, n: usize) -> Reg<Fcclksel, RW>

Flexcomm Interface 0 clock source select for Fractional Rate Divider

pub const fn hslspiclksel(self) -> Reg<Hslspiclksel, RW>

HS LSPI clock source select

pub const fn mclkclksel(self) -> Reg<Mclkclksel, RW>

MCLK clock source select

pub const fn sctclksel(self) -> Reg<Sctclksel, RW>

SCTimer/PWM clock source select

pub const fn systickclkdiv0(self) -> Reg<Systickclkdiv0, RW>

System Tick Timer divider for CPU0

pub const fn traceclkdiv(self) -> Reg<Traceclkdiv, RW>

TRACE clock divider

pub const fn canclkdiv(self) -> Reg<Canclkdiv, RW>

CAN clock divider

pub const fn flexfrgctrl(self, n: usize) -> Reg<Flexfrgctrl, RW>

Fractional rate divider for flexcomm 0

pub const fn flexfrgxctrl(self, n: usize) -> Reg<Flexfrgxctrl, RW>

Peripheral reset control register

pub const fn ahbclkdiv(self) -> Reg<Ahbclkdiv, RW>

System clock divider

pub const fn clkoutdiv(self) -> Reg<Clkoutdiv, RW>

CLKOUT clock divider

pub const fn frohfdiv(self) -> Reg<Frohfdiv, RW>

FRO_HF (96MHz) clock divider

pub const fn wdtclkdiv(self) -> Reg<Wdtclkdiv, RW>

WDT clock divider

pub const fn adcclkdiv(self) -> Reg<Adcclkdiv, RW>

ADC clock divider

pub const fn usb0clkdiv(self) -> Reg<Usb0clkdiv, RW>

USB0-FS Clock divider

pub const fn fro1mclkdiv(self) -> Reg<Fro1mclkdiv, RW>

FRO1MHz Clock divider (FRO1M_divided)

pub const fn mclkdiv(self) -> Reg<Mclkdiv, RW>

I2S MCLK clock divider

pub const fn sctclkdiv(self) -> Reg<Sctclkdiv, RW>

SCT/PWM clock divider

pub const fn pll0clkdiv(self) -> Reg<Pll0clkdiv, RW>

PLL0 clock divider

pub const fn clockgenupdatelockout(self) -> Reg<Clockgenupdatelockout, RW>

Control clock configuration registers access (like xxxDIV, xxxSEL)

pub const fn fmccr(self) -> Reg<Fmccr, RW>

FMC configuration register

pub const fn usb0needclkctrl(self) -> Reg<Usb0needclkctrl, RW>

USB0-FS need clock control

pub const fn usb0needclkstat(self) -> Reg<Usb0needclkstat, RW>

USB0-FS need clock status

pub const fn fmcflush(self) -> Reg<Fmcflush, W>

FMCflush control

pub const fn mclkio(self) -> Reg<Mclkio, RW>

MCLK control

pub const fn usb1needclkctrl(self) -> Reg<Usb1needclkctrl, RW>

USB1-HS need clock control

pub const fn usb1needclkstat(self) -> Reg<Usb1needclkstat, RW>

USB1-HS need clock status

pub const fn flashremap_size(self) -> Reg<FlashremapSize, RW>

This 32-bit register contains the size of the image to remap, in bytes. The 12 LSBs are ignored, so the size granularity is 4KB.

pub const fn flashremap_size_dp(self) -> Reg<FlashremapSizeDp, RW>

This 32-bit register is a duplicate of FLASHREMAPSIZE for increased security.

pub const fn flashremap_offset(self) -> Reg<FlashremapOffset, RW>

This 32-bit register contains the offset by which the image is to be remapped. The 12 LSBs are ignored, so the remap granularity is 4KB.

pub const fn flashremap_offset_dp(self) -> Reg<FlashremapOffsetDp, RW>

This 32-bit register is a duplicate of FLASHREMAPOFFSET for increased security.

pub const fn flashremap_lock(self) -> Reg<FlashremapLock, RW>

Control write access to FLASHREMAP_SIZE and FLASHREMAP_OFFSET registers.

pub const fn casper_ctrl(self) -> Reg<CasperCtrl, RW>

Control CASPER integration.

pub const fn pll1ctrl(self) -> Reg<Pll1ctrl, RW>

PLL1 550m control

pub const fn pll1stat(self) -> Reg<Pll1stat, RW>

PLL1 550m status

pub const fn pll1ndec(self) -> Reg<Pll1ndec, RW>

PLL1 550m N divider

pub const fn pll1mdec(self) -> Reg<Pll1mdec, RW>

PLL1 550m M divider

pub const fn pll1pdec(self) -> Reg<Pll1pdec, RW>

PLL1 550m P divider

pub const fn pll0ctrl(self) -> Reg<Pll0ctrl, RW>

PLL0 550m control

pub const fn pll0stat(self) -> Reg<Pll0stat, RW>

PLL0 550m status

pub const fn pll0ndec(self) -> Reg<Pll0ndec, RW>

PLL0 550m N divider

pub const fn pll0pdec(self) -> Reg<Pll0pdec, RW>

PLL0 550m P divider

pub const fn pll0sscg0(self) -> Reg<Pll0sscg0, RW>

PLL0 Spread Spectrum Wrapper control register 0

pub const fn pll0sscg1(self) -> Reg<Pll0sscg1, RW>

PLL0 Spread Spectrum Wrapper control register 1

pub const fn funcretentionctrl(self) -> Reg<Funcretentionctrl, RW>

Functional retention control register

pub const fn cpstat(self) -> Reg<Cpstat, RW>

CPU Status

pub const fn boot_seed_reg0(self) -> Reg<BootSeedReg0, RW>

boot seed (256-bit random value)

pub const fn boot_seed_reg1(self) -> Reg<BootSeedReg1, RW>

boot seed (256-bit random value)

pub const fn boot_seed_reg2(self) -> Reg<BootSeedReg2, RW>

boot seed (256-bit random value)

pub const fn boot_seed_reg3(self) -> Reg<BootSeedReg3, RW>

boot seed (256-bit random value)

pub const fn boot_seed_reg4(self) -> Reg<BootSeedReg4, RW>

boot seed (256-bit random value)

pub const fn boot_seed_reg5(self) -> Reg<BootSeedReg5, RW>

boot seed (256-bit random value)

pub const fn boot_seed_reg6(self) -> Reg<BootSeedReg6, RW>

boot seed (256-bit random value)

pub const fn boot_seed_reg7(self) -> Reg<BootSeedReg7, RW>

boot seed (256-bit random value)

pub const fn hmac_reg0(self) -> Reg<HmacReg0, RW>

HMAC

pub const fn hmac_reg1(self) -> Reg<HmacReg1, RW>

HMAC

pub const fn hmac_reg2(self) -> Reg<HmacReg2, RW>

HMAC

pub const fn hmac_reg3(self) -> Reg<HmacReg3, RW>

HMAC

pub const fn hmac_reg4(self) -> Reg<HmacReg4, RW>

HMAC

pub const fn hmac_reg5(self) -> Reg<HmacReg5, RW>

HMAC

pub const fn hmac_reg6(self) -> Reg<HmacReg6, RW>

HMAC

pub const fn hmac_reg7(self) -> Reg<HmacReg7, RW>

HMAC

pub const fn boot_lock(self) -> Reg<BootLock, RW>

Control write access to boot seed security registers.

pub const fn clock_ctrl(self) -> Reg<ClockCtrl, RW>

Various system clock controls : Flash clock (48 MHz) control, clocks to Frequency Measures

pub const fn comp_int_ctrl(self) -> Reg<CompIntCtrl, RW>

Comparator Interrupt control

pub const fn comp_int_status(self) -> Reg<CompIntStatus, RW>

Comparator Interrupt status

pub const fn autoclkgateoverride(self) -> Reg<Autoclkgateoverride, RW>

Control automatic clock gating

pub const fn gpiopsync(self) -> Reg<Gpiopsync, RW>

Enable bypass of the first stage of synchonization inside GPIO_INT module

pub const fn hashresthwkey(self) -> Reg<Hashresthwkey, RW>

Controls whether the HASH AES hardware secret key is restricted to use by secure code

pub const fn debug_lock_en(self) -> Reg<DebugLockEn, RW>

Control write access to security registers.

pub const fn debug_features(self) -> Reg<DebugFeatures, RW>

Cortex debug features control.

pub const fn debug_features_dp(self) -> Reg<DebugFeaturesDp, RW>

Cortex debug features control. (duplicate)

pub const fn swd_access_cpu0(self) -> Reg<SwdAccessCpu0, RW>

This register is used by ROM during DEBUG authentication mechanism to enable debug access port for CPU0.

pub const fn key_block(self) -> Reg<KeyBlock, W>

block quiddikey/PUF all index.

pub const fn debug_auth_beacon(self) -> Reg<DebugAuthBeacon, RW>

Debug authentication BEACON register

pub const fn device_id0(self) -> Reg<DeviceId0, R>

Device ID

pub const fn dieid(self) -> Reg<Dieid, R>

Chip revision ID and Number

Trait Implementations

impl Clone for Syscon

fn clone(&self) -> Syscon

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl PartialEq for Syscon

fn eq(&self, other: &Syscon) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Syscon

impl Eq for Syscon

impl Send for Syscon

impl StructuralPartialEq for Syscon

impl Sync for Syscon