#[repr(transparent)]pub struct Ctrl(pub u32);Expand description
Control register to enable and operate Hash and Crypto
Tuple Fields§
§0: u32Implementations§
Source§impl Ctrl
impl Ctrl
Sourcepub const fn mode(&self) -> Mode
pub const fn mode(&self) -> Mode
The operational mode to use, or 0 if none. Note that the CONFIG register will indicate if specific modes beyond SHA1 and SHA2-256 are available.
Sourcepub const fn set_mode(&mut self, val: Mode)
pub const fn set_mode(&mut self, val: Mode)
The operational mode to use, or 0 if none. Note that the CONFIG register will indicate if specific modes beyond SHA1 and SHA2-256 are available.
Sourcepub const fn new_hash(&self) -> bool
pub const fn new_hash(&self) -> bool
Written with 1 when starting a new Hash/Crypto. It self clears. Note that the WAITING Status bit will clear for a cycle during the initialization from New=1.
Sourcepub const fn set_new_hash(&mut self, val: bool)
pub const fn set_new_hash(&mut self, val: bool)
Written with 1 when starting a new Hash/Crypto. It self clears. Note that the WAITING Status bit will clear for a cycle during the initialization from New=1.
Sourcepub const fn dma_i(&self) -> DmaI
pub const fn dma_i(&self) -> DmaI
Written with 1 to use DMA to fill INDATA. If Hash, will request from DMA for 16 words and then will process the Hash. If Cryptographic, it will load as many words as needed, including key if not already loaded. It will then request again. Normal model is that the DMA interrupts the processor when its length expires. Note that if the processor will write the key and optionally IV, it should not enable this until it has done so. Otherwise, the DMA will be expected to load those for the 1st block (when needed).
Sourcepub const fn set_dma_i(&mut self, val: DmaI)
pub const fn set_dma_i(&mut self, val: DmaI)
Written with 1 to use DMA to fill INDATA. If Hash, will request from DMA for 16 words and then will process the Hash. If Cryptographic, it will load as many words as needed, including key if not already loaded. It will then request again. Normal model is that the DMA interrupts the processor when its length expires. Note that if the processor will write the key and optionally IV, it should not enable this until it has done so. Otherwise, the DMA will be expected to load those for the 1st block (when needed).
Sourcepub const fn dma_o(&self) -> bool
pub const fn dma_o(&self) -> bool
Written to 1 to use DMA to drain the digest/output. If both DMA_I and DMA_O are set, the DMA has to know to switch direction and the locations. This can be used for crypto uses.
Sourcepub const fn set_dma_o(&mut self, val: bool)
pub const fn set_dma_o(&mut self, val: bool)
Written to 1 to use DMA to drain the digest/output. If both DMA_I and DMA_O are set, the DMA has to know to switch direction and the locations. This can be used for crypto uses.
Sourcepub const fn hashswpb(&self) -> bool
pub const fn hashswpb(&self) -> bool
If 1, will swap bytes in the word for SHA hashing. The default is byte order (so LSB is 1st byte) but this allows swapping to MSB is 1st such as is shown in SHS spec. For cryptographic swapping, see the CRYPTCFG register.
Sourcepub const fn set_hashswpb(&mut self, val: bool)
pub const fn set_hashswpb(&mut self, val: bool)
If 1, will swap bytes in the word for SHA hashing. The default is byte order (so LSB is 1st byte) but this allows swapping to MSB is 1st such as is shown in SHS spec. For cryptographic swapping, see the CRYPTCFG register.