Struct Port1Pcr0 

#[repr(transparent)]
pub struct Port1Pcr0(pub u32);

Pin Control 0.

Tuple Fields

0: u32

Implementations

impl Port1Pcr0

pub const fn ps(&self) -> Port1Pcr0Ps

Pull Select.

pub const fn set_ps(&mut self, val: Port1Pcr0Ps)

Pull Select.

pub const fn pe(&self) -> Port1Pcr0Pe

Pull Enable.

pub const fn set_pe(&mut self, val: Port1Pcr0Pe)

Pull Enable.

pub const fn sre(&self) -> Port1Pcr0Sre

Slew Rate Enable.

pub const fn set_sre(&mut self, val: Port1Pcr0Sre)

Slew Rate Enable.

pub const fn pfe(&self) -> Port1Pcr0Pfe

Passive Filter Enable.

pub const fn set_pfe(&mut self, val: Port1Pcr0Pfe)

Passive Filter Enable.

pub const fn ode(&self) -> Port1Pcr0Ode

Open Drain Enable.

pub const fn set_ode(&mut self, val: Port1Pcr0Ode)

Open Drain Enable.

pub const fn dse(&self) -> Port1Pcr0Dse

Drive Strength Enable.

pub const fn set_dse(&mut self, val: Port1Pcr0Dse)

Drive Strength Enable.

pub const fn mux(&self) -> Port1Pcr0Mux

Pin Multiplex Control.

pub const fn set_mux(&mut self, val: Port1Pcr0Mux)

Pin Multiplex Control.

pub const fn ibe(&self) -> Port1Pcr0Ibe

Input Buffer Enable.

pub const fn set_ibe(&mut self, val: Port1Pcr0Ibe)

Input Buffer Enable.

pub const fn inv(&self) -> Port1Pcr0Inv

Invert Input.

pub const fn set_inv(&mut self, val: Port1Pcr0Inv)

Invert Input.

pub const fn lk(&self) -> Port1Pcr0Lk

Lock Register.

pub const fn set_lk(&mut self, val: Port1Pcr0Lk)

Lock Register.

Trait Implementations

impl Clone for Port1Pcr0

fn clone(&self) -> Port1Pcr0

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for Port1Pcr0

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Default for Port1Pcr0

fn default() -> Port1Pcr0

Returns the “default value” for a type.

impl PartialEq for Port1Pcr0

fn eq(&self, other: &Port1Pcr0) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Port1Pcr0

impl Eq for Port1Pcr0

impl StructuralPartialEq for Port1Pcr0