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Module flexpwm

Module flexpwm 

Source
Expand description

Peripheral access API (generated using chiptool v0.1.0 (e890244 2026-11-05))

Structs§

Dtsrcsel
PWM Source Select Register.
Fctrl0
Fault Control Register.
Fctrl20
Fault Control 2 Register.
Ffilt0
Fault Filter Register.
Flexpwm
Enhanced Flex Pulse Width Modulator (eFlexPWM).
Flexpwm1
Enhanced Flex Pulse Width Modulator (eFlexPWM).
Flexpwm1Dtsrcsel
PWM Source Select Register.
Flexpwm1Fctrl0
Fault Control Register.
Flexpwm1Fctrl20
Fault Control 2 Register.
Flexpwm1Ffilt0
Fault Filter Register.
Flexpwm1Fsts0
Fault Status Register.
Flexpwm1Ftst0
Fault Test Register.
Flexpwm1Mask
Mask Register.
Flexpwm1Mctrl
Master Control Register.
Flexpwm1Mctrl2
Master Control 2 Register.
Flexpwm1Outen
Output Enable Register.
Flexpwm1Sm0captcompx
Capture Compare X Register.
Flexpwm1Sm0captctrlx
Capture Control X Register.
Flexpwm1Sm0captfiltx
Capture PWM_X Input Filter Register.
Flexpwm1Sm0cnt
Counter Register.
Flexpwm1Sm0ctrl
Control Register.
Flexpwm1Sm0ctrl2
Control 2 Register.
Flexpwm1Sm0cval0
Capture Value 0 Register.
Flexpwm1Sm0cval0cyc
Capture Value 0 Cycle Register.
Flexpwm1Sm0cval1
Capture Value 1 Register.
Flexpwm1Sm0cval1cyc
Capture Value 1 Cycle Register.
Flexpwm1Sm0dismap0
Fault Disable Mapping Register 0.
Flexpwm1Sm0dmaen
DMA Enable Register.
Flexpwm1Sm0dtcnt0
Deadtime Count Register 0.
Flexpwm1Sm0dtcnt1
Deadtime Count Register 1.
Flexpwm1Sm0init
Initial Count Register.
Flexpwm1Sm0inten
Interrupt Enable Register.
Flexpwm1Sm0octrl
Output Control Register.
Flexpwm1Sm0sts
Status Register.
Flexpwm1Sm0tctrl
Output Trigger Control Register.
Flexpwm1Sm0val0
Value Register 0.
Flexpwm1Sm0val1
Value Register 1.
Flexpwm1Sm0val2
Value Register 2.
Flexpwm1Sm0val3
Value Register 3.
Flexpwm1Sm0val4
Value Register 4.
Flexpwm1Sm0val5
Value Register 5.
Flexpwm1Sm1captcompx
Capture Compare X Register.
Flexpwm1Sm1captctrlx
Capture Control X Register.
Flexpwm1Sm1captfiltx
Capture PWM_X Input Filter Register.
Flexpwm1Sm1cnt
Counter Register.
Flexpwm1Sm1ctrl
Control Register.
Flexpwm1Sm1ctrl2
Control 2 Register.
Flexpwm1Sm1cval0
Capture Value 0 Register.
Flexpwm1Sm1cval0cyc
Capture Value 0 Cycle Register.
Flexpwm1Sm1cval1
Capture Value 1 Register.
Flexpwm1Sm1cval1cyc
Capture Value 1 Cycle Register.
Flexpwm1Sm1dismap0
Fault Disable Mapping Register 0.
Flexpwm1Sm1dmaen
DMA Enable Register.
Flexpwm1Sm1dtcnt0
Deadtime Count Register 0.
Flexpwm1Sm1dtcnt1
Deadtime Count Register 1.
Flexpwm1Sm1init
Initial Count Register.
Flexpwm1Sm1inten
Interrupt Enable Register.
Flexpwm1Sm1octrl
Output Control Register.
Flexpwm1Sm1phasedly
Phase Delay Register.
Flexpwm1Sm1sts
Status Register.
Flexpwm1Sm1tctrl
Output Trigger Control Register.
Flexpwm1Sm1val0
Value Register 0.
Flexpwm1Sm1val1
Value Register 1.
Flexpwm1Sm1val2
Value Register 2.
Flexpwm1Sm1val3
Value Register 3.
Flexpwm1Sm1val4
Value Register 4.
Flexpwm1Sm1val5
Value Register 5.
Flexpwm1Sm2captcompx
Capture Compare X Register.
Flexpwm1Sm2captctrlx
Capture Control X Register.
Flexpwm1Sm2captfiltx
Capture PWM_X Input Filter Register.
Flexpwm1Sm2cnt
Counter Register.
Flexpwm1Sm2ctrl
Control Register.
Flexpwm1Sm2ctrl2
Control 2 Register.
Flexpwm1Sm2cval0
Capture Value 0 Register.
Flexpwm1Sm2cval0cyc
Capture Value 0 Cycle Register.
Flexpwm1Sm2cval1
Capture Value 1 Register.
Flexpwm1Sm2cval1cyc
Capture Value 1 Cycle Register.
Flexpwm1Sm2dismap0
Fault Disable Mapping Register 0.
Flexpwm1Sm2dmaen
DMA Enable Register.
Flexpwm1Sm2dtcnt0
Deadtime Count Register 0.
Flexpwm1Sm2dtcnt1
Deadtime Count Register 1.
Flexpwm1Sm2init
Initial Count Register.
Flexpwm1Sm2inten
Interrupt Enable Register.
Flexpwm1Sm2octrl
Output Control Register.
Flexpwm1Sm2phasedly
Phase Delay Register.
Flexpwm1Sm2sts
Status Register.
Flexpwm1Sm2tctrl
Output Trigger Control Register.
Flexpwm1Sm2val0
Value Register 0.
Flexpwm1Sm2val1
Value Register 1.
Flexpwm1Sm2val2
Value Register 2.
Flexpwm1Sm2val3
Value Register 3.
Flexpwm1Sm2val4
Value Register 4.
Flexpwm1Sm2val5
Value Register 5.
Flexpwm1Sm3cnt
Counter Register.
Flexpwm1Sm3ctrl
Control Register.
Flexpwm1Sm3ctrl2
Control 2 Register.
Flexpwm1Sm3dismap0
Fault Disable Mapping Register 0.
Flexpwm1Sm3dmaen
DMA Enable Register.
Flexpwm1Sm3dtcnt0
Deadtime Count Register 0.
Flexpwm1Sm3dtcnt1
Deadtime Count Register 1.
Flexpwm1Sm3init
Initial Count Register.
Flexpwm1Sm3inten
Interrupt Enable Register.
Flexpwm1Sm3octrl
Output Control Register.
Flexpwm1Sm3phasedly
Phase Delay Register.
Flexpwm1Sm3sts
Status Register.
Flexpwm1Sm3tctrl
Output Trigger Control Register.
Flexpwm1Sm3val0
Value Register 0.
Flexpwm1Sm3val1
Value Register 1.
Flexpwm1Sm3val2
Value Register 2.
Flexpwm1Sm3val3
Value Register 3.
Flexpwm1Sm3val4
Value Register 4.
Flexpwm1Sm3val5
Value Register 5.
Flexpwm1Swcout
Software Controlled Output Register.
Fsts0
Fault Status Register.
Ftst0
Fault Test Register.
Mask
Mask Register.
Mctrl
Master Control Register.
Mctrl2
Master Control 2 Register.
Outen
Output Enable Register.
Sm0captcompx
Capture Compare X Register.
Sm0captctrlx
Capture Control X Register.
Sm0captfiltx
Capture PWM_X Input Filter Register.
Sm0cnt
Counter Register.
Sm0ctrl
Control Register.
Sm0ctrl2
Control 2 Register.
Sm0cval0
Capture Value 0 Register.
Sm0cval0cyc
Capture Value 0 Cycle Register.
Sm0cval1
Capture Value 1 Register.
Sm0cval1cyc
Capture Value 1 Cycle Register.
Sm0dismap0
Fault Disable Mapping Register 0.
Sm0dmaen
DMA Enable Register.
Sm0dtcnt0
Deadtime Count Register 0.
Sm0dtcnt1
Deadtime Count Register 1.
Sm0init
Initial Count Register.
Sm0inten
Interrupt Enable Register.
Sm0octrl
Output Control Register.
Sm0sts
Status Register.
Sm0tctrl
Output Trigger Control Register.
Sm0val0
Value Register 0.
Sm0val1
Value Register 1.
Sm0val2
Value Register 2.
Sm0val3
Value Register 3.
Sm0val4
Value Register 4.
Sm0val5
Value Register 5.
Sm1captcompx
Capture Compare X Register.
Sm1captctrlx
Capture Control X Register.
Sm1captfiltx
Capture PWM_X Input Filter Register.
Sm1cnt
Counter Register.
Sm1ctrl
Control Register.
Sm1ctrl2
Control 2 Register.
Sm1cval0
Capture Value 0 Register.
Sm1cval0cyc
Capture Value 0 Cycle Register.
Sm1cval1
Capture Value 1 Register.
Sm1cval1cyc
Capture Value 1 Cycle Register.
Sm1dismap0
Fault Disable Mapping Register 0.
Sm1dmaen
DMA Enable Register.
Sm1dtcnt0
Deadtime Count Register 0.
Sm1dtcnt1
Deadtime Count Register 1.
Sm1init
Initial Count Register.
Sm1inten
Interrupt Enable Register.
Sm1octrl
Output Control Register.
Sm1phasedly
Phase Delay Register.
Sm1sts
Status Register.
Sm1tctrl
Output Trigger Control Register.
Sm1val0
Value Register 0.
Sm1val1
Value Register 1.
Sm1val2
Value Register 2.
Sm1val3
Value Register 3.
Sm1val4
Value Register 4.
Sm1val5
Value Register 5.
Sm2captcompx
Capture Compare X Register.
Sm2captctrlx
Capture Control X Register.
Sm2captfiltx
Capture PWM_X Input Filter Register.
Sm2cnt
Counter Register.
Sm2ctrl
Control Register.
Sm2ctrl2
Control 2 Register.
Sm2cval0
Capture Value 0 Register.
Sm2cval0cyc
Capture Value 0 Cycle Register.
Sm2cval1
Capture Value 1 Register.
Sm2cval1cyc
Capture Value 1 Cycle Register.
Sm2dismap0
Fault Disable Mapping Register 0.
Sm2dmaen
DMA Enable Register.
Sm2dtcnt0
Deadtime Count Register 0.
Sm2dtcnt1
Deadtime Count Register 1.
Sm2init
Initial Count Register.
Sm2inten
Interrupt Enable Register.
Sm2octrl
Output Control Register.
Sm2phasedly
Phase Delay Register.
Sm2sts
Status Register.
Sm2tctrl
Output Trigger Control Register.
Sm2val0
Value Register 0.
Sm2val1
Value Register 1.
Sm2val2
Value Register 2.
Sm2val3
Value Register 3.
Sm2val4
Value Register 4.
Sm2val5
Value Register 5.
Sm3captcompx
Capture Compare X Register.
Sm3captctrlx
Capture Control X Register.
Sm3captfiltx
Capture PWM_X Input Filter Register.
Sm3cnt
Counter Register.
Sm3ctrl
Control Register.
Sm3ctrl2
Control 2 Register.
Sm3cval0
Capture Value 0 Register.
Sm3cval0cyc
Capture Value 0 Cycle Register.
Sm3cval1
Capture Value 1 Register.
Sm3cval1cyc
Capture Value 1 Cycle Register.
Sm3dismap0
Fault Disable Mapping Register 0.
Sm3dmaen
DMA Enable Register.
Sm3dtcnt0
Deadtime Count Register 0.
Sm3dtcnt1
Deadtime Count Register 1.
Sm3init
Initial Count Register.
Sm3inten
Interrupt Enable Register.
Sm3octrl
Output Control Register.
Sm3phasedly
Phase Delay Register.
Sm3sts
Status Register.
Sm3tctrl
Output Trigger Control Register.
Sm3val0
Value Register 0.
Sm3val1
Value Register 1.
Sm3val2
Value Register 2.
Sm3val3
Value Register 3.
Sm3val4
Value Register 4.
Sm3val5
Value Register 5.
Swcout
Software Controlled Output Register.

Enums§

Fauto
Fflag
Ffull
Fhalf
Fie
Flexpwm1Fauto
Flexpwm1Fflag
Flexpwm1Ffull
Flexpwm1Fhalf
Flexpwm1Fie
Flexpwm1Flvl
Flexpwm1Fsafe
Flexpwm1Ipol
Flexpwm1Ldok
Flexpwm1Nocomb
Flexpwm1Run
Flexpwm1Sm0captctrlxEdgx0
Flexpwm1Sm0captctrlxEdgx1
Flexpwm1Sm0captctrlxInpSelx
Flexpwm1Sm0captctrlxOneshotx
Flexpwm1Sm0ctrl2ClkSel
Flexpwm1Sm0ctrl2ForceSel
Flexpwm1Sm0ctrl2Indep
Flexpwm1Sm0ctrl2InitSel
Flexpwm1Sm0ctrl2ReloadSel
Flexpwm1Sm0ctrlCompmode
Flexpwm1Sm0ctrlLdfq
Flexpwm1Sm0ctrlLdmod
Flexpwm1Sm0ctrlPrsc
Flexpwm1Sm0dmaenCaptde
Flexpwm1Sm0dmaenFand
Flexpwm1Sm0intenCmpie
Flexpwm1Sm0octrlPwmafs
Flexpwm1Sm0octrlPwmbfs
Flexpwm1Sm0octrlPwmxfs
Flexpwm1Sm0out23
Flexpwm1Sm0out45
Flexpwm1Sm0sel23
Flexpwm1Sm0sel45
Flexpwm1Sm0stsCmpf
Flexpwm1Sm0tctrlOutTrigEn
Flexpwm1Sm0tctrlPwaot0
Flexpwm1Sm0tctrlPwbot1
Flexpwm1Sm0tctrlTrgfrq
Flexpwm1Sm1captctrlxEdgx0
Flexpwm1Sm1captctrlxEdgx1
Flexpwm1Sm1captctrlxInpSelx
Flexpwm1Sm1captctrlxOneshotx
Flexpwm1Sm1ctrl2ClkSel
Flexpwm1Sm1ctrl2ForceSel
Flexpwm1Sm1ctrl2Indep
Flexpwm1Sm1ctrl2InitSel
Flexpwm1Sm1ctrl2ReloadSel
Flexpwm1Sm1ctrlCompmode
Flexpwm1Sm1ctrlLdfq
Flexpwm1Sm1ctrlLdmod
Flexpwm1Sm1ctrlPrsc
Flexpwm1Sm1dmaenCaptde
Flexpwm1Sm1dmaenFand
Flexpwm1Sm1intenCmpie
Flexpwm1Sm1octrlPwmafs
Flexpwm1Sm1octrlPwmbfs
Flexpwm1Sm1octrlPwmxfs
Flexpwm1Sm1out23
Flexpwm1Sm1out45
Flexpwm1Sm1sel23
Flexpwm1Sm1sel45
Flexpwm1Sm1stsCmpf
Flexpwm1Sm1tctrlOutTrigEn
Flexpwm1Sm1tctrlPwaot0
Flexpwm1Sm1tctrlPwbot1
Flexpwm1Sm1tctrlTrgfrq
Flexpwm1Sm2captctrlxEdgx0
Flexpwm1Sm2captctrlxEdgx1
Flexpwm1Sm2captctrlxInpSelx
Flexpwm1Sm2captctrlxOneshotx
Flexpwm1Sm2ctrl2ClkSel
Flexpwm1Sm2ctrl2ForceSel
Flexpwm1Sm2ctrl2Indep
Flexpwm1Sm2ctrl2InitSel
Flexpwm1Sm2ctrl2ReloadSel
Flexpwm1Sm2ctrlCompmode
Flexpwm1Sm2ctrlLdfq
Flexpwm1Sm2ctrlLdmod
Flexpwm1Sm2ctrlPrsc
Flexpwm1Sm2dmaenCaptde
Flexpwm1Sm2dmaenFand
Flexpwm1Sm2intenCmpie
Flexpwm1Sm2octrlPwmafs
Flexpwm1Sm2octrlPwmbfs
Flexpwm1Sm2octrlPwmxfs
Flexpwm1Sm2out23
Flexpwm1Sm2out45
Flexpwm1Sm2sel23
Flexpwm1Sm2sel45
Flexpwm1Sm2stsCmpf
Flexpwm1Sm2tctrlOutTrigEn
Flexpwm1Sm2tctrlPwaot0
Flexpwm1Sm2tctrlPwbot1
Flexpwm1Sm2tctrlTrgfrq
Flexpwm1Sm3ctrl2ClkSel
Flexpwm1Sm3ctrl2ForceSel
Flexpwm1Sm3ctrl2Indep
Flexpwm1Sm3ctrl2InitSel
Flexpwm1Sm3ctrl2ReloadSel
Flexpwm1Sm3ctrlCompmode
Flexpwm1Sm3ctrlLdfq
Flexpwm1Sm3ctrlLdmod
Flexpwm1Sm3ctrlPrsc
Flexpwm1Sm3dmaenCaptde
Flexpwm1Sm3dmaenFand
Flexpwm1Sm3intenCmpie
Flexpwm1Sm3octrlPwmafs
Flexpwm1Sm3octrlPwmbfs
Flexpwm1Sm3octrlPwmxfs
Flexpwm1Sm3out23
Flexpwm1Sm3out45
Flexpwm1Sm3sel23
Flexpwm1Sm3sel45
Flexpwm1Sm3stsCmpf
Flexpwm1Sm3tctrlOutTrigEn
Flexpwm1Sm3tctrlPwaot0
Flexpwm1Sm3tctrlPwbot1
Flexpwm1Sm3tctrlTrgfrq
Flexpwm1StretchCntPrsc
Flexpwm1Wrprot
Flvl
Fsafe
Ipol
Ldok
Nocomb
Run
Sm0captctrlxEdgx0
Sm0captctrlxEdgx1
Sm0captctrlxInpSelx
Sm0captctrlxOneshotx
Sm0ctrl2ClkSel
Sm0ctrl2ForceSel
Sm0ctrl2Indep
Sm0ctrl2InitSel
Sm0ctrl2ReloadSel
Sm0ctrlCompmode
Sm0ctrlLdfq
Sm0ctrlLdmod
Sm0ctrlPrsc
Sm0dmaenCaptde
Sm0dmaenFand
Sm0intenCmpie
Sm0octrlPwmafs
Sm0octrlPwmbfs
Sm0octrlPwmxfs
Sm0out23
Sm0out45
Sm0sel23
Sm0sel45
Sm0stsCmpf
Sm0tctrlOutTrigEn
Sm0tctrlPwaot0
Sm0tctrlPwbot1
Sm0tctrlTrgfrq
Sm1captctrlxEdgx0
Sm1captctrlxEdgx1
Sm1captctrlxInpSelx
Sm1captctrlxOneshotx
Sm1ctrl2ClkSel
Sm1ctrl2ForceSel
Sm1ctrl2Indep
Sm1ctrl2InitSel
Sm1ctrl2ReloadSel
Sm1ctrlCompmode
Sm1ctrlLdfq
Sm1ctrlLdmod
Sm1ctrlPrsc
Sm1dmaenCaptde
Sm1dmaenFand
Sm1intenCmpie
Sm1octrlPwmafs
Sm1octrlPwmbfs
Sm1octrlPwmxfs
Sm1out23
Sm1out45
Sm1sel23
Sm1sel45
Sm1stsCmpf
Sm1tctrlOutTrigEn
Sm1tctrlPwaot0
Sm1tctrlPwbot1
Sm1tctrlTrgfrq
Sm2captctrlxEdgx0
Sm2captctrlxEdgx1
Sm2captctrlxInpSelx
Sm2captctrlxOneshotx
Sm2ctrl2ClkSel
Sm2ctrl2ForceSel
Sm2ctrl2Indep
Sm2ctrl2InitSel
Sm2ctrl2ReloadSel
Sm2ctrlCompmode
Sm2ctrlLdfq
Sm2ctrlLdmod
Sm2ctrlPrsc
Sm2dmaenCaptde
Sm2dmaenFand
Sm2intenCmpie
Sm2octrlPwmafs
Sm2octrlPwmbfs
Sm2octrlPwmxfs
Sm2out23
Sm2out45
Sm2sel23
Sm2sel45
Sm2stsCmpf
Sm2tctrlOutTrigEn
Sm2tctrlPwaot0
Sm2tctrlPwbot1
Sm2tctrlTrgfrq
Sm3captctrlxEdgx0
Sm3captctrlxEdgx1
Sm3captctrlxInpSelx
Sm3captctrlxOneshotx
Sm3ctrl2ClkSel
Sm3ctrl2ForceSel
Sm3ctrl2Indep
Sm3ctrl2InitSel
Sm3ctrl2ReloadSel
Sm3ctrlCompmode
Sm3ctrlLdfq
Sm3ctrlLdmod
Sm3ctrlPrsc
Sm3dmaenCaptde
Sm3dmaenFand
Sm3intenCmpie
Sm3octrlPwmafs
Sm3octrlPwmbfs
Sm3octrlPwmxfs
Sm3out23
Sm3out45
Sm3sel23
Sm3sel45
Sm3stsCmpf
Sm3tctrlOutTrigEn
Sm3tctrlPwaot0
Sm3tctrlPwbot1
Sm3tctrlTrgfrq
StretchCntPrsc
Wrprot