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Flexpwm1

nxp_pac::flexpwm

Struct Flexpwm1 

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pub struct Flexpwm1 { /* private fields */ }
Expand description

Enhanced Flex Pulse Width Modulator (eFlexPWM).

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impl Flexpwm1

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pub const unsafe fn from_ptr(ptr: *mut ()) -> Self

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pub const fn as_ptr(&self) -> *mut ()

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pub const fn sm0cnt(self) -> Reg<Flexpwm1Sm0cnt, R>

Counter Register.

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pub const fn sm0init(self) -> Reg<Flexpwm1Sm0init, RW>

Initial Count Register.

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pub const fn sm0ctrl2(self) -> Reg<Flexpwm1Sm0ctrl2, RW>

Control 2 Register.

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pub const fn sm0ctrl(self) -> Reg<Flexpwm1Sm0ctrl, RW>

Control Register.

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pub const fn sm0val0(self) -> Reg<Flexpwm1Sm0val0, RW>

Value Register 0.

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pub const fn sm0val1(self) -> Reg<Flexpwm1Sm0val1, RW>

Value Register 1.

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pub const fn sm0val2(self) -> Reg<Flexpwm1Sm0val2, RW>

Value Register 2.

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pub const fn sm0val3(self) -> Reg<Flexpwm1Sm0val3, RW>

Value Register 3.

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pub const fn sm0val4(self) -> Reg<Flexpwm1Sm0val4, RW>

Value Register 4.

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pub const fn sm0val5(self) -> Reg<Flexpwm1Sm0val5, RW>

Value Register 5.

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pub const fn sm0octrl(self) -> Reg<Flexpwm1Sm0octrl, RW>

Output Control Register.

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pub const fn sm0sts(self) -> Reg<Flexpwm1Sm0sts, RW>

Status Register.

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pub const fn sm0inten(self) -> Reg<Flexpwm1Sm0inten, RW>

Interrupt Enable Register.

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pub const fn sm0dmaen(self) -> Reg<Flexpwm1Sm0dmaen, RW>

DMA Enable Register.

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pub const fn sm0tctrl(self) -> Reg<Flexpwm1Sm0tctrl, RW>

Output Trigger Control Register.

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pub const fn sm0dismap0(self) -> Reg<Flexpwm1Sm0dismap0, RW>

Fault Disable Mapping Register 0.

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pub const fn sm0dtcnt0(self) -> Reg<Flexpwm1Sm0dtcnt0, RW>

Deadtime Count Register 0.

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pub const fn sm0dtcnt1(self) -> Reg<Flexpwm1Sm0dtcnt1, RW>

Deadtime Count Register 1.

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pub const fn sm0captctrlx(self) -> Reg<Flexpwm1Sm0captctrlx, RW>

Capture Control X Register.

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pub const fn sm0captcompx(self) -> Reg<Flexpwm1Sm0captcompx, RW>

Capture Compare X Register.

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pub const fn sm0cval0(self) -> Reg<Flexpwm1Sm0cval0, R>

Capture Value 0 Register.

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pub const fn sm0cval0cyc(self) -> Reg<Flexpwm1Sm0cval0cyc, R>

Capture Value 0 Cycle Register.

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pub const fn sm0cval1(self) -> Reg<Flexpwm1Sm0cval1, R>

Capture Value 1 Register.

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pub const fn sm0cval1cyc(self) -> Reg<Flexpwm1Sm0cval1cyc, R>

Capture Value 1 Cycle Register.

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pub const fn sm0captfiltx(self) -> Reg<Flexpwm1Sm0captfiltx, RW>

Capture PWM_X Input Filter Register.

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pub const fn sm1cnt(self) -> Reg<Flexpwm1Sm1cnt, R>

Counter Register.

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pub const fn sm1init(self) -> Reg<Flexpwm1Sm1init, RW>

Initial Count Register.

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pub const fn sm1ctrl2(self) -> Reg<Flexpwm1Sm1ctrl2, RW>

Control 2 Register.

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pub const fn sm1ctrl(self) -> Reg<Flexpwm1Sm1ctrl, RW>

Control Register.

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pub const fn sm1val0(self) -> Reg<Flexpwm1Sm1val0, RW>

Value Register 0.

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pub const fn sm1val1(self) -> Reg<Flexpwm1Sm1val1, RW>

Value Register 1.

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pub const fn sm1val2(self) -> Reg<Flexpwm1Sm1val2, RW>

Value Register 2.

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pub const fn sm1val3(self) -> Reg<Flexpwm1Sm1val3, RW>

Value Register 3.

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pub const fn sm1val4(self) -> Reg<Flexpwm1Sm1val4, RW>

Value Register 4.

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pub const fn sm1val5(self) -> Reg<Flexpwm1Sm1val5, RW>

Value Register 5.

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pub const fn sm1octrl(self) -> Reg<Flexpwm1Sm1octrl, RW>

Output Control Register.

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pub const fn sm1sts(self) -> Reg<Flexpwm1Sm1sts, RW>

Status Register.

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pub const fn sm1inten(self) -> Reg<Flexpwm1Sm1inten, RW>

Interrupt Enable Register.

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pub const fn sm1dmaen(self) -> Reg<Flexpwm1Sm1dmaen, RW>

DMA Enable Register.

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pub const fn sm1tctrl(self) -> Reg<Flexpwm1Sm1tctrl, RW>

Output Trigger Control Register.

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pub const fn sm1dismap0(self) -> Reg<Flexpwm1Sm1dismap0, RW>

Fault Disable Mapping Register 0.

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pub const fn sm1dtcnt0(self) -> Reg<Flexpwm1Sm1dtcnt0, RW>

Deadtime Count Register 0.

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pub const fn sm1dtcnt1(self) -> Reg<Flexpwm1Sm1dtcnt1, RW>

Deadtime Count Register 1.

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pub const fn sm1captctrlx(self) -> Reg<Flexpwm1Sm1captctrlx, RW>

Capture Control X Register.

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pub const fn sm1captcompx(self) -> Reg<Flexpwm1Sm1captcompx, RW>

Capture Compare X Register.

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pub const fn sm1cval0(self) -> Reg<Flexpwm1Sm1cval0, R>

Capture Value 0 Register.

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pub const fn sm1cval0cyc(self) -> Reg<Flexpwm1Sm1cval0cyc, R>

Capture Value 0 Cycle Register.

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pub const fn sm1cval1(self) -> Reg<Flexpwm1Sm1cval1, R>

Capture Value 1 Register.

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pub const fn sm1cval1cyc(self) -> Reg<Flexpwm1Sm1cval1cyc, R>

Capture Value 1 Cycle Register.

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pub const fn sm1phasedly(self) -> Reg<Flexpwm1Sm1phasedly, RW>

Phase Delay Register.

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pub const fn sm1captfiltx(self) -> Reg<Flexpwm1Sm1captfiltx, RW>

Capture PWM_X Input Filter Register.

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pub const fn sm2cnt(self) -> Reg<Flexpwm1Sm2cnt, R>

Counter Register.

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pub const fn sm2init(self) -> Reg<Flexpwm1Sm2init, RW>

Initial Count Register.

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pub const fn sm2ctrl2(self) -> Reg<Flexpwm1Sm2ctrl2, RW>

Control 2 Register.

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pub const fn sm2ctrl(self) -> Reg<Flexpwm1Sm2ctrl, RW>

Control Register.

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pub const fn sm2val0(self) -> Reg<Flexpwm1Sm2val0, RW>

Value Register 0.

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pub const fn sm2val1(self) -> Reg<Flexpwm1Sm2val1, RW>

Value Register 1.

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pub const fn sm2val2(self) -> Reg<Flexpwm1Sm2val2, RW>

Value Register 2.

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pub const fn sm2val3(self) -> Reg<Flexpwm1Sm2val3, RW>

Value Register 3.

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pub const fn sm2val4(self) -> Reg<Flexpwm1Sm2val4, RW>

Value Register 4.

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pub const fn sm2val5(self) -> Reg<Flexpwm1Sm2val5, RW>

Value Register 5.

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pub const fn sm2octrl(self) -> Reg<Flexpwm1Sm2octrl, RW>

Output Control Register.

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pub const fn sm2sts(self) -> Reg<Flexpwm1Sm2sts, RW>

Status Register.

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pub const fn sm2inten(self) -> Reg<Flexpwm1Sm2inten, RW>

Interrupt Enable Register.

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pub const fn sm2dmaen(self) -> Reg<Flexpwm1Sm2dmaen, RW>

DMA Enable Register.

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pub const fn sm2tctrl(self) -> Reg<Flexpwm1Sm2tctrl, RW>

Output Trigger Control Register.

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pub const fn sm2dismap0(self) -> Reg<Flexpwm1Sm2dismap0, RW>

Fault Disable Mapping Register 0.

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pub const fn sm2dtcnt0(self) -> Reg<Flexpwm1Sm2dtcnt0, RW>

Deadtime Count Register 0.

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pub const fn sm2dtcnt1(self) -> Reg<Flexpwm1Sm2dtcnt1, RW>

Deadtime Count Register 1.

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pub const fn sm2captctrlx(self) -> Reg<Flexpwm1Sm2captctrlx, RW>

Capture Control X Register.

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pub const fn sm2captcompx(self) -> Reg<Flexpwm1Sm2captcompx, RW>

Capture Compare X Register.

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pub const fn sm2cval0(self) -> Reg<Flexpwm1Sm2cval0, R>

Capture Value 0 Register.

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pub const fn sm2cval0cyc(self) -> Reg<Flexpwm1Sm2cval0cyc, R>

Capture Value 0 Cycle Register.

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pub const fn sm2cval1(self) -> Reg<Flexpwm1Sm2cval1, R>

Capture Value 1 Register.

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pub const fn sm2cval1cyc(self) -> Reg<Flexpwm1Sm2cval1cyc, R>

Capture Value 1 Cycle Register.

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pub const fn sm2phasedly(self) -> Reg<Flexpwm1Sm2phasedly, RW>

Phase Delay Register.

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pub const fn sm2captfiltx(self) -> Reg<Flexpwm1Sm2captfiltx, RW>

Capture PWM_X Input Filter Register.

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pub const fn sm3cnt(self) -> Reg<Flexpwm1Sm3cnt, R>

Counter Register.

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pub const fn sm3init(self) -> Reg<Flexpwm1Sm3init, RW>

Initial Count Register.

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pub const fn sm3ctrl2(self) -> Reg<Flexpwm1Sm3ctrl2, RW>

Control 2 Register.

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pub const fn sm3ctrl(self) -> Reg<Flexpwm1Sm3ctrl, RW>

Control Register.

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pub const fn sm3val0(self) -> Reg<Flexpwm1Sm3val0, RW>

Value Register 0.

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pub const fn sm3val1(self) -> Reg<Flexpwm1Sm3val1, RW>

Value Register 1.

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pub const fn sm3val2(self) -> Reg<Flexpwm1Sm3val2, RW>

Value Register 2.

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pub const fn sm3val3(self) -> Reg<Flexpwm1Sm3val3, RW>

Value Register 3.

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pub const fn sm3val4(self) -> Reg<Flexpwm1Sm3val4, RW>

Value Register 4.

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pub const fn sm3val5(self) -> Reg<Flexpwm1Sm3val5, RW>

Value Register 5.

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pub const fn sm3octrl(self) -> Reg<Flexpwm1Sm3octrl, RW>

Output Control Register.

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pub const fn sm3sts(self) -> Reg<Flexpwm1Sm3sts, RW>

Status Register.

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pub const fn sm3inten(self) -> Reg<Flexpwm1Sm3inten, RW>

Interrupt Enable Register.

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pub const fn sm3dmaen(self) -> Reg<Flexpwm1Sm3dmaen, RW>

DMA Enable Register.

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pub const fn sm3tctrl(self) -> Reg<Flexpwm1Sm3tctrl, RW>

Output Trigger Control Register.

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pub const fn sm3dismap0(self) -> Reg<Flexpwm1Sm3dismap0, RW>

Fault Disable Mapping Register 0.

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pub const fn sm3dtcnt0(self) -> Reg<Flexpwm1Sm3dtcnt0, RW>

Deadtime Count Register 0.

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pub const fn sm3dtcnt1(self) -> Reg<Flexpwm1Sm3dtcnt1, RW>

Deadtime Count Register 1.

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pub const fn sm3phasedly(self) -> Reg<Flexpwm1Sm3phasedly, RW>

Phase Delay Register.

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pub const fn outen(self) -> Reg<Flexpwm1Outen, RW>

Output Enable Register.

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pub const fn mask(self) -> Reg<Flexpwm1Mask, RW>

Mask Register.

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pub const fn swcout(self) -> Reg<Flexpwm1Swcout, RW>

Software Controlled Output Register.

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pub const fn dtsrcsel(self) -> Reg<Flexpwm1Dtsrcsel, RW>

PWM Source Select Register.

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pub const fn mctrl(self) -> Reg<Flexpwm1Mctrl, RW>

Master Control Register.

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pub const fn mctrl2(self) -> Reg<Flexpwm1Mctrl2, RW>

Master Control 2 Register.

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pub const fn fctrl0(self) -> Reg<Flexpwm1Fctrl0, RW>

Fault Control Register.

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pub const fn fsts0(self) -> Reg<Flexpwm1Fsts0, RW>

Fault Status Register.

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pub const fn ffilt0(self) -> Reg<Flexpwm1Ffilt0, RW>

Fault Filter Register.

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pub const fn ftst0(self) -> Reg<Flexpwm1Ftst0, RW>

Fault Test Register.

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pub const fn fctrl20(self) -> Reg<Flexpwm1Fctrl20, RW>

Fault Control 2 Register.

Trait Implementations§

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impl Clone for Flexpwm1

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fn clone(&self) -> Flexpwm1

Returns a duplicate of the value. Read more
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fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source. Read more
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impl PartialEq for Flexpwm1

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fn eq(&self, other: &Flexpwm1) -> bool

Tests for self and other values to be equal, and is used by ==.
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fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.
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impl Copy for Flexpwm1

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impl Eq for Flexpwm1

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impl Send for Flexpwm1

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impl StructuralPartialEq for Flexpwm1

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impl Sync for Flexpwm1

Auto Trait Implementations§

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impl<T> Any for T
where T: 'static + ?Sized,

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fn type_id(&self) -> TypeId

Gets the TypeId of self. Read more
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impl<T> Borrow<T> for T
where T: ?Sized,

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fn borrow(&self) -> &T

Immutably borrows from an owned value. Read more
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impl<T> BorrowMut<T> for T
where T: ?Sized,

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fn borrow_mut(&mut self) -> &mut T

Mutably borrows from an owned value. Read more
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impl<T> CloneToUninit for T
where T: Clone,

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unsafe fn clone_to_uninit(&self, dest: *mut u8)

🔬This is a nightly-only experimental API. (clone_to_uninit)
Performs copy-assignment from self to dest. Read more
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impl<T> From<T> for T

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fn from(t: T) -> T

Returns the argument unchanged.

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impl<T, U> Into<U> for T
where U: From<T>,

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fn into(self) -> U

Calls U::from(self).

That is, this conversion is whatever the implementation of From<T> for U chooses to do.

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impl<T, U> TryFrom<U> for T
where U: Into<T>,

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type Error = Infallible

The type returned in the event of a conversion error.
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fn try_from(value: U) -> Result<T, <T as TryFrom<U>>::Error>

Performs the conversion.
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impl<T, U> TryInto<U> for T
where U: TryFrom<T>,

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type Error = <U as TryFrom<T>>::Error

The type returned in the event of a conversion error.
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fn try_into(self) -> Result<U, <U as TryFrom<T>>::Error>

Performs the conversion.