#[repr(u8)]pub enum Shcycle {
Clk64 = 0,
Clk128 = 1,
}Variants§
Clk64 = 0
Sample & hold phase clock period is 64 LCD clock (16kHz) period / 32 LCD clock (8kHz) period.
Clk128 = 1
Sample & hold phase clock period is 128 LCD clk (16kHz) period / 64 LCD clock (8kHz) period.
Implementations§
Trait Implementations§
Source§impl Ord for Shcycle
impl Ord for Shcycle
Source§impl PartialOrd for Shcycle
impl PartialOrd for Shcycle
impl Copy for Shcycle
impl Eq for Shcycle
impl StructuralPartialEq for Shcycle
Auto Trait Implementations§
impl Freeze for Shcycle
impl RefUnwindSafe for Shcycle
impl Send for Shcycle
impl Sync for Shcycle
impl Unpin for Shcycle
impl UnwindSafe for Shcycle
Blanket Implementations§
Source§impl<T> BorrowMut<T> for Twhere
T: ?Sized,
impl<T> BorrowMut<T> for Twhere
T: ?Sized,
Source§fn borrow_mut(&mut self) -> &mut T
fn borrow_mut(&mut self) -> &mut T
Mutably borrows from an owned value. Read more