#[repr(u8)]pub enum Flexpwm1Fsafe {
Show 16 variants
Normal = 0,
Safe = 1,
_RESERVED_2 = 2,
_RESERVED_3 = 3,
_RESERVED_4 = 4,
_RESERVED_5 = 5,
_RESERVED_6 = 6,
_RESERVED_7 = 7,
_RESERVED_8 = 8,
_RESERVED_9 = 9,
_RESERVED_a = 10,
_RESERVED_b = 11,
_RESERVED_c = 12,
_RESERVED_d = 13,
_RESERVED_e = 14,
_RESERVED_f = 15,
}Variants§
Normal = 0
Normal mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear at the start of a half cycle or full cycle depending on the states of FSTS[FHALF] and FSTS[FFULL] without regard to the state of FSTS[FFPINx]. If neither FHALF nor FFULL is set, then the fault condition cannot be cleared. The PWM outputs disabled by this fault input will not be re-enabled until the actual FAULTx input signal de-asserts since the fault input will combinationally disable the PWM outputs (as programmed in DISMAPn).
Safe = 1
Safe mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear and FSTS[FFPINx] is clear at the start of a half cycle or full cycle depending on the states of FSTS[FHALF] and FSTS[FFULL]. If neither FHLAF nor FFULL is set, then the fault condition cannot be cleared.
_RESERVED_2 = 2
_RESERVED_3 = 3
_RESERVED_4 = 4
_RESERVED_5 = 5
_RESERVED_6 = 6
_RESERVED_7 = 7
_RESERVED_8 = 8
_RESERVED_9 = 9
_RESERVED_a = 10
_RESERVED_b = 11
_RESERVED_c = 12
_RESERVED_d = 13
_RESERVED_e = 14
_RESERVED_f = 15
Implementations§
Source§impl Flexpwm1Fsafe
impl Flexpwm1Fsafe
Trait Implementations§
Source§impl Clone for Flexpwm1Fsafe
impl Clone for Flexpwm1Fsafe
Source§fn clone(&self) -> Flexpwm1Fsafe
fn clone(&self) -> Flexpwm1Fsafe
1.0.0 · Source§fn clone_from(&mut self, source: &Self)
fn clone_from(&mut self, source: &Self)
source. Read more